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From:   Michael Walle <michael@walle.cc>
To:     Linus Walleij <linus.walleij@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Lars Povlsen <lars.povlsen@microchip.com>
Cc:     linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Horatiu Vultur <horatiu.vultur@microchip.com>,
        Michael Walle <michael@walle.cc>
Subject: [PATCH v2 0/2] pinctrl: ocelot: add shared reset
Date:   Wed, 20 Apr 2022 01:03:22 +0200
Message-Id: <20220419230324.3221779-1-michael@walle.cc>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

On LAN966x SoCs, there is an internal reset which is used to reset the
switch core. But this will also reset the GPIO and the SGPIO. Thus add
support for this shared reset line.

changes since v1:
 - rebased onto linus' devel tree, former patch was still based on
   v1 of the YAML conversion patch

Michael Walle (2):
  dt-bindings: pinctrl: ocelot: add reset property
  pinctrl: ocelot: add optional shared reset

 .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 8 ++++++++
 drivers/pinctrl/pinctrl-ocelot.c                         | 9 +++++++++
 2 files changed, 17 insertions(+)

-- 
2.30.2