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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id n3-20020a05620a152300b0069ec409e679sm2651317qkk.48.2022.04.21.02.31.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Apr 2022 02:31:12 -0700 (PDT) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-2eafabbc80aso45557967b3.11; Thu, 21 Apr 2022 02:31:12 -0700 (PDT) X-Received: by 2002:a81:c703:0:b0:2d0:cc6b:3092 with SMTP id m3-20020a81c703000000b002d0cc6b3092mr24791356ywi.449.1650533472388; Thu, 21 Apr 2022 02:31:12 -0700 (PDT) MIME-Version: 1.0 References: <20220414122250.158113-1-clement.leger@bootlin.com> <20220414122250.158113-11-clement.leger@bootlin.com> In-Reply-To: <20220414122250.158113-11-clement.leger@bootlin.com> From: Geert Uytterhoeven Date: Thu, 21 Apr 2022 11:31:01 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH net-next 10/12] ARM: dts: r9a06g032: describe GMAC2 To: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Magnus Damm , Heiner Kallweit , Russell King , Thomas Petazzoni , Herve Codina , =?UTF-8?Q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Linux Kernel Mailing List , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas , netdev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Clément, On Thu, Apr 14, 2022 at 2:24 PM Clément Léger wrote: > RZ/N1 SoC includes two MAC named GMACx that are compatible with the > "snps,dwmac" driver. GMAC1 is connected directly to the MII converter > port 1. GMAC2 however can be used as the MAC for the switch CPU > management port or can be muxed to be connected directly to the MII > converter port 2. This commit add description for the GMAC2 which will > be used by the switch description. > > Signed-off-by: Clément Léger Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -200,6 +200,23 @@ nand_controller: nand-controller@40102000 { > status = "disabled"; > }; > > + gmac2: ethernet@44002000 { > + compatible = "snps,dwmac-3.72a", "snps,dwmac"; "make dtbs_check": arch/arm/boot/dts/r9a06g032-rzn1d400-db.dtb:0:0: /soc/ethernet@44002000: failed to match any schema with compatible: ['snps,dwmac-3.72a', 'snps,dwmac'] > + reg = <0x44002000 0x2000>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + ; > + interrupt-names = "macirq", "eth_lpi", "eth_wake_irq"; arch/arm/boot/dts/r9a06g032-rzn1d400-db.dtb: ethernet@44002000: interrupt-names:1: 'eth_wake_irq' was expected arch/arm/boot/dts/r9a06g032-rzn1d400-db.dtb: ethernet@44002000: interrupt-names:2: 'eth_lpi' was expected From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml > + clock-names = "stmmaceth"; > + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; > + snps,multicast-filter-bins = <256>; > + snps,perfect-filter-entries = <128>; > + tx-fifo-depth = <2048>; > + rx-fifo-depth = <4096>; > + status = "disabled"; > + }; > + > eth_miic: eth-miic@44030000 { > compatible = "renesas,rzn1-miic"; > #address-cells = <1>; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds