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Date:   Wed, 20 Apr 2022 07:56:44 +0200
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Subject: Re: [PATCH 1/2] EDAC: synopsys: Add disable_intr support for V3.X
 Synopsys EDAC DDR
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To:     Sherry Sun <sherry.sun@nxp.com>, <bp@alien8.de>,
        <mchehab@kernel.org>, <michal.simek@xilinx.com>,
        <tony.luck@intel.com>, <james.morse@arm.com>, <rric@kernel.org>
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        <linux-arm-kernel@lists.infradead.org>, <linux-imx@nxp.com>
References: <20220318111742.15730-1-sherry.sun@nxp.com>
 <20220318111742.15730-2-sherry.sun@nxp.com>
From:   Michal Simek <michal.simek@xilinx.com>
In-Reply-To: <20220318111742.15730-2-sherry.sun@nxp.com>
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On 3/18/22 12:17, Sherry Sun wrote:
> V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
> to change to use the ECC Clear Register to disable the interrupts.
> 
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>   drivers/edac/synopsys_edac.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> index f05ff02c0656..1b630f0be119 100644
> --- a/drivers/edac/synopsys_edac.c
> +++ b/drivers/edac/synopsys_edac.c
> @@ -859,8 +859,11 @@ static void enable_intr(struct synps_edac_priv *priv)
>   static void disable_intr(struct synps_edac_priv *priv)
>   {
>   	/* Disable UE/CE Interrupts */
> -	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> -			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
> +	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
> +		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
> +	else
> +		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> +		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
>   }
>   
>   static int setup_irq(struct mem_ctl_info *mci,

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal