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Miller" Content-Type: text/plain; charset="UTF-8" X-Provags-ID: V03:K1:LVaoYcR/yzXToY4XQaCHMihnNd9WPKphM0R6+jq7LKxEFQeaGVz cvs2k21UEkXLzY/XqUx8f4IMkeeLQG54lmzG6HtZXAleGsvaSS9jAgAjxvvq8JTwyd0JGAh ZTJHaLED0VjixU//FV6R+JGvWRDiFsEvEKcPkhosUupCAFsjfQ46mjoOSmHYJID+yKwMZjy uWN9YKdQQLG5ZXzBU216A== X-UI-Out-Filterresults: notjunk:1;V03:K0:N7gcqfY2yGQ=:zUyyN9MiHDuco6NNg9SUIw xORNvRLX1N6Z/yt+sk6TaqePLr5pe6bxx/pM5+PQVaKjSjeESkJK0Jbrr9TEHJCJrvTVXBPZ7 Mrgm34m+NAbmgD5M31kAaqnZhBC6VuAsApd52OnQ7z+jR6TNiZ8fCP714ZDWb704PuGQh0BhG G9FJTGl8qKOIMR34aHEwjWuQT32x/Ndwttcn9kvVimdQnnpCsvEQzuR4DGHBvrCUoSjoEnIbC Tz54sUiVvnJixr6BcO5egJjPAGgPEwwNRK5gj9eWOMxDsHH2MFvszx8BbrxDIedI+41jG91wK IC3wLzFZ9Nfva3+BmjAfwrMM3NO17s429zb2HmTzvHhppF1tf0k1b2D69IfzaVTk0fNRBViTz pM3G8yEBhdpeWe9GVJdTuw1V4TNlixr2UZQa2P+tKkKk3+DN4sP0rNR/mtxV8bFkHH3J2xdNF yJAvqB1TBFHzDgqRkLyqsRMGnrFqzthSAG14WmJ59v45COBBCC0vtUBt/hi2A8MPDApOn9she k66v1ENFHdrcdYTpw568RjSA1wWnyt0BNMBvHrjumufjRHIGT4hWpe5uZhMsl+JqqrvI59Fx5 L8RXOYq8I2/PZ1OGSww8sNTF1PZiksfc4WtTFD43yG/nyTgvhX5mBQbxeEjjY86GXDMrIl7sO 4EzRv2jmrCi3TgrtAUbamXjKpzILPOtbZwbq7dxkl2Aejs3peoumymiSwjZsby2+1opf550xh bNhosKnEHpuaBu6I9IL9koQF8QQywFZy2ZoRhf3f94vgINcxhuJA0s5Q50IKtl9oIuBT8Fe25 EqF/CWUsnUzkzEcqa9E0rUKGikGWalJ2WI/CEQDOYWhkTPzOJ4= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 21, 2022 at 4:44 PM Catalin Marinas wrote: > On Thu, Apr 21, 2022 at 03:47:30PM +0200, Arnd Bergmann wrote: > > On Thu, Apr 21, 2022 at 3:25 PM Catalin Marinas wrote: > > > On Thu, Apr 21, 2022 at 02:28:45PM +0200, Arnd Bergmann wrote: > > > > We also know that larger slabs are all cacheline aligned, so simply > > > > comparing the transfer size is enough to rule out most, in this case > > > > any transfer larger than 96 bytes must come from the kmalloc-128 > > > > or larger cache, so that works like before. > > > > > > There's also the case with 128-byte cache lines and kmalloc-192. > > > > Sure, but that's much less common, as the few machines with 128 byte > > cache lines tend to also have cache coherent devices IIRC, so we'd > > skip the bounce buffer entirely. > > Do you know which machines still have 128-byte cache lines _and_ > non-coherent DMA? If there isn't any that matters, I'd reduce > ARCH_DMA_MINALIGN to 64 now (while trying to get to even smaller kmalloc > caches). I think the last time this came up, someone pointed out one of the Qualcomm Snapdragon phone chips with their custom cores. Arnd