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[23.128.96.19]) by mx.google.com with ESMTPS id q11-20020a65494b000000b0039d9d404482si9462010pgs.570.2022.04.22.10.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 10:42:58 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=bvjQbMrl; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CE8B3CA0EA; Fri, 22 Apr 2022 10:30:33 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357732AbiDSUxR (ORCPT + 99 others); Tue, 19 Apr 2022 16:53:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233556AbiDSUxP (ORCPT ); Tue, 19 Apr 2022 16:53:15 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BB413E5D4; Tue, 19 Apr 2022 13:50:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1650401432; x=1681937432; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=Mxl40I/GVF4LYfYnv2CrUGvPyjKo5X9LbQFOPvAimOY=; b=bvjQbMrlqNmENjrVbwCendq0ch5CGvA2YEArOj6eOdJ5lx0pmERLR/D+ eyOqsB2xznhDzDn1rsTgi0Xb/GbDeB1y115AJ/+NoHHUvi/r7HBe37cAW Rv1yvF0SdfUhqgeLwD/HCsaI2qpb15nsv9dVgx6G1CvDq2czypOFYenvU g=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 19 Apr 2022 13:50:32 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2022 13:50:32 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 19 Apr 2022 13:50:31 -0700 Received: from [10.111.175.117] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 19 Apr 2022 13:50:28 -0700 Message-ID: Date: Tue, 19 Apr 2022 13:50:26 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v7 08/14] drm/msm/dpu: don't use merge_3d if DSC merge topology is used Content-Language: en-US To: Vinod Koul , Rob Clark CC: , Bjorn Andersson , Dmitry Baryshkov , David Airlie , Daniel Vetter , "Jonathan Marek" , , , References: <20220406094031.1027376-1-vkoul@kernel.org> <20220406094031.1027376-9-vkoul@kernel.org> From: Abhinav Kumar In-Reply-To: <20220406094031.1027376-9-vkoul@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/6/2022 2:40 AM, Vinod Koul wrote: > From: Dmitry Baryshkov > > DPU supports different topologies for the case when multiple INTFs are > being driven by the single phys_enc. The driver defaults to using 3DMux > in such cases. Don't use it if DSC merge is used instead. > > Suggested-by: Abhinav Kumar > Signed-off-by: Dmitry Baryshkov > Signed-off-by: Vinod Koul Thank you for making the change generic as suggested. Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 ++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 6 ++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4 +++- > 3 files changed, 25 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 4052486f19d8..95d1588f3bb6 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -511,6 +511,22 @@ void dpu_encoder_helper_split_config( > } > } > > +bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) > +{ > + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); > + int i, intf_count = 0, num_dsc = 0; > + > + for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) > + if (dpu_enc->phys_encs[i]) > + intf_count++; > + > + /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ > + if (dpu_enc->dsc) > + num_dsc = 2; > + > + return (num_dsc > 0) && (num_dsc > intf_count); > +} > + > static struct msm_display_topology dpu_encoder_get_topology( > struct dpu_encoder_virt *dpu_enc, > struct dpu_kms *dpu_kms, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h > index ef873e5285a0..084c5265d7e5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h > @@ -172,4 +172,10 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc); > */ > int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc); > > +/** > + * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. > + * @drm_enc: Pointer to previously created drm encoder structure > + */ > +bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc); > + > #endif /* __DPU_ENCODER_H__ */ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index 4842070fdfa8..b5ad43b8a19b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -314,8 +314,10 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( > > dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); > > + /* Use merge_3d unless DSC MERGE topology is used */ > if (phys_enc->split_role == ENC_ROLE_SOLO && > - dpu_cstate->num_mixers == CRTC_DUAL_MIXERS) > + dpu_cstate->num_mixers == CRTC_DUAL_MIXERS && > + !dpu_encoder_use_dsc_merge(phys_enc->parent)) > return BLEND_3D_H_ROW_INT; > > return BLEND_3D_NONE;