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From:   Krishna Reddy <vdumpa@nvidia.com>
To:     Ashish Mhetre <amhetre@nvidia.com>,
        "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
        "will@kernel.org" <will@kernel.org>,
        "robin.murphy@arm.com" <robin.murphy@arm.com>,
        "joro@8bytes.org" <joro@8bytes.org>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     Sachin Nikam <Snikam@nvidia.com>,
        Nicolin Chen <nicolinc@nvidia.com>,
        Pritesh Raithatha <praithatha@nvidia.com>
Subject: RE: [Patch v2] iommu: arm-smmu: disable large page mappings for
 Nvidia arm-smmu
Thread-Topic: [Patch v2] iommu: arm-smmu: disable large page mappings for
 Nvidia arm-smmu
Thread-Index: AQHYVVf8weZxvKTC30eHfb8NPTIKIKz6j93Q
Date:   Thu, 21 Apr 2022 16:34:29 +0000
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References: <20220421081504.24678-1-amhetre@nvidia.com>
In-Reply-To: <20220421081504.24678-1-amhetre@nvidia.com>
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> Tegra194 and Tegra234 SoCs have the erratum that causes walk cache entrie=
s to
> not be invalidated correctly. The problem is that the walk cache index ge=
nerated
> for IOVA is not same across translation and invalidation requests. This i=
s leading
> to page faults when PMD entry is released during unmap and populated with
> new PTE table during subsequent map request. Disabling large page mapping=
s
> avoids the release of PMD entry and avoid translations seeing stale PMD e=
ntry in
> walk cache.
> Fix this by limiting the page mappings to PAGE_SIZE for Tegra194 and
> Tegra234 devices. This is recommended fix from Tegra hardware design team=
.
>=20
> Co-developed-by: Pritesh Raithatha <praithatha@nvidia.com>
> Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
> ---
> Changes in v2:
> - Using init_context() to override pgsize_bitmap instead of new function
>=20
>  drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 30
> ++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>=20
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> index 01e9b50b10a1..87bf522b9d2e 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> @@ -258,6 +258,34 @@ static void nvidia_smmu_probe_finalize(struct
> arm_smmu_device *smmu, struct devi
>  			dev_name(dev), err);
>  }
>=20
> +static int nvidia_smmu_init_context(struct arm_smmu_domain
> *smmu_domain,
> +				    struct io_pgtable_cfg *pgtbl_cfg,
> +				    struct device *dev)
> +{
> +	struct arm_smmu_device *smmu =3D smmu_domain->smmu;
> +	const struct device_node *np =3D smmu->dev->of_node;
> +
> +	/*
> +	 * Tegra194 and Tegra234 SoCs have the erratum that causes walk
> cache
> +	 * entries to not be invalidated correctly. The problem is that the wal=
k
> +	 * cache index generated for IOVA is not same across translation and
> +	 * invalidation requests. This is leading to page faults when PMD entry
> +	 * is released during unmap and populated with new PTE table during
> +	 * subsequent map request. Disabling large page mappings avoids the
> +	 * release of PMD entry and avoid translations seeing stale PMD entry i=
n
> +	 * walk cache.
> +	 * Fix this by limiting the page mappings to PAGE_SIZE on Tegra194 and
> +	 * Tegra234.
> +	 */
> +	if (of_device_is_compatible(np, "nvidia,tegra234-smmu") ||
> +	    of_device_is_compatible(np, "nvidia,tegra194-smmu")) {
> +		smmu->pgsize_bitmap =3D PAGE_SIZE;
> +		pgtbl_cfg->pgsize_bitmap =3D smmu->pgsize_bitmap;
> +	}
> +
> +	return 0;
> +}
> +
>  static const struct arm_smmu_impl nvidia_smmu_impl =3D {
>  	.read_reg =3D nvidia_smmu_read_reg,
>  	.write_reg =3D nvidia_smmu_write_reg,
> @@ -268,10 +296,12 @@ static const struct arm_smmu_impl
> nvidia_smmu_impl =3D {
>  	.global_fault =3D nvidia_smmu_global_fault,
>  	.context_fault =3D nvidia_smmu_context_fault,
>  	.probe_finalize =3D nvidia_smmu_probe_finalize,
> +	.init_context =3D nvidia_smmu_init_context,
>  };
>=20
>  static const struct arm_smmu_impl nvidia_smmu_single_impl =3D {
>  	.probe_finalize =3D nvidia_smmu_probe_finalize,
> +	.init_context =3D nvidia_smmu_init_context,
>  };
>=20

Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

-KR