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[92.40.203.64]) by smtp.gmail.com with ESMTPSA id p3-20020adfaa03000000b00207a1db96cfsm2185493wrd.71.2022.04.22.08.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 08:53:20 -0700 (PDT) Date: Fri, 22 Apr 2022 16:54:10 +0100 From: Aidan MacDonald To: Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, mturquette@baylibre.com, paul@crapouillou.net, paulburton@kernel.org, tsbogend@alpha.franken.de Subject: Re: [RESEND PATCH 2/3] clk: ingenic: Mark critical clocks in Ingenic SoCs Message-ID: References: <20220411101441.17020-1-aidanmacdonald.0x0@gmail.com> <20220411101441.17020-3-aidanmacdonald.0x0@gmail.com> <20220422023359.87E8FC385A8@smtp.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220422023359.87E8FC385A8@smtp.kernel.org> X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RDNS_NONE, SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 21, 2022 at 07:33:57PM -0700, Stephen Boyd wrote: > Quoting Aidan MacDonald (2022-04-11 03:14:40) > > Consider the CPU, L2 cache, and memory as critical to ensure they > > are not disabled. > > > > Signed-off-by: Aidan MacDonald > > Reviewed-by: Paul Cercueil > > --- > > General comment, please add a comment around CLK_IS_CRITICAL usage if it > isn't very clear why such a clk shouldn't be turned off. Second, is > there any point in describing these clks in the kernel and using memory > to do that if they're just going to always be on? Wouldn't a dummy clk > returned from clk_get() work just as well if anything is grabbing a > reference with clk_get()? I'd guess they're there to keep track of which PLLs are in use, at least for SoCs that have more than one PLL. Using a dummy clock sounds like a bad idea since it won't represent that, and besides the clock configuration is something that can change at runtime so hardcoding it would be foolish. I'll send a v2 with explanatory comments around CLK_IS_CRITICAL. Regards, Aidan