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References: <20220421192132.109954-1-nick.hawkins@hpe.com> <20220421192132.109954-2-nick.hawkins@hpe.com>
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From:   Arnd Bergmann <arnd@arndb.de>
Date:   Fri, 22 Apr 2022 15:20:11 +0200
Message-ID: <CAK8P3a0E4=8Drn_x19MkauNL_WC4vEL6wqkDqrafbT-n8cZpDA@mail.gmail.com>
Subject: Re: [PATCH v5 01/11] archh: arm: mach-hpe: Introduce the HPE GXP architecture
To:     "Hawkins, Nick" <nick.hawkins@hpe.com>
Cc:     "Verdun, Jean-Marie" <verdun@hpe.com>,
        Joel Stanley <joel@jms.id.au>, Arnd Bergmann <arnd@arndb.de>,
        OpenBMC Maillist <openbmc@lists.ozlabs.org>,
        Russell King <linux@armlinux.org.uk>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Thu, Apr 21, 2022 at 9:21 PM <nick.hawkins@hpe.com> wrote:
> +
> +DT_MACHINE_START(GXP_DT, "HPE GXP")
> +       .dt_compat      = gxp_board_dt_compat,
> +       .l2c_aux_val = 0,
> +       .l2c_aux_mask = 0,
> +MACHINE_END

Ther l2c initialization looks wrong here, where  you are saying here is
that all the bits of the aux register must be set to zero.

I also see that you don't have a device node for the cache controller, so
this is probably not actually used, but in general there should be one with
the correct properties.

        Arnd