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From:   "tarumizu.kohei@fujitsu.com" <tarumizu.kohei@fujitsu.com>
To:     'Thomas Gleixner' <tglx@linutronix.de>,
        "catalin.marinas@arm.com" <catalin.marinas@arm.com>,
        "will@kernel.org" <will@kernel.org>,
        "mingo@redhat.com" <mingo@redhat.com>,
        "bp@alien8.de" <bp@alien8.de>,
        "dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
        "x86@kernel.org" <x86@kernel.org>, "hpa@zytor.com" <hpa@zytor.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "fenghua.yu@intel.com" <fenghua.yu@intel.com>,
        "reinette.chatre@intel.com" <reinette.chatre@intel.com>
Subject: RE: [PATCH v3 7/9] x86: Add hardware prefetch control support for x86
Thread-Topic: [PATCH v3 7/9] x86: Add hardware prefetch control support for
 x86
Thread-Index: AQHYVGMS5ZVzEyeIOE2a6l/c0xocPaz5YsWAgAJ4j6A=
Date:   Fri, 22 Apr 2022 12:16:18 +0000
Message-ID: <OSBPR01MB2037FFD9250ED3E075E2778080F79@OSBPR01MB2037.jpnprd01.prod.outlook.com>
References: <20220420030223.689259-1-tarumizu.kohei@fujitsu.com>
 <20220420030223.689259-8-tarumizu.kohei@fujitsu.com> <87czhbtmpu.ffs@tglx>
In-Reply-To: <87czhbtmpu.ffs@tglx>
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> Prefetch control is supported on a lot of CPU models and all except Xeon =
PHI have
> the same MSR layout. ATOMs do not support L2_ACL and DCU_IP, but that's i=
t. So
> there is absolutely nothing broadwell specific here.
>=20
> Why do we need six explicit functions, which are pretty much copy and pas=
te?

There is no special reason for them. My design was not good.

> The only difference is the bit they operate on. It's just a matter of pro=
per wrapper
> structs.
>=20
> See? One show() and one store() function which operates directly at the a=
ttribute
> level and supports all known variants of bits in the control MSR. No magi=
c global
> constants, no visible management, no hardcoded type/level relations... Si=
mple
> and straight forward.
>=20
> All what the core code needs to do is to populate the attributes in the
> sys/.../cache/index$N/ directories when level and type matches.
>=20
> I'm pretty sure you can simplify the A64FX code in a very similar way.

Thank you for showing me a concrete example. The implementation image
is now clear. With this in mind, I would like to simplify the core,
x86 and A64FX codes.