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Subject: Re: [PATCH v2 1/2] dt-bindings: clock: Add Qualcomm SC8280XP GCC bindings
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        quic_tdas@quicinc.com
To:     Bjorn Andersson <bjorn.andersson@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>
Date:   Fri, 22 Apr 2022 18:48:22 -0700
User-Agent: alot/0.10
Message-Id: <20220423014824.912ACC385A0@smtp.kernel.org>
Precedence: bulk

Quoting Bjorn Andersson (2022-04-22 16:00:12)
> Add binding for the Qualcomm SC8280XP Global Clock controller.
>=20
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Why no cover letter?

> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.ya=
ml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> new file mode 100644
> index 000000000000..44e5f0d0a795
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> @@ -0,0 +1,199 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
> +
> +maintainers:
> +  - Bjorn Andersson <bjorn.andersson@linaro.org>
> +
> +description: |
> +  Qualcomm global clock control module which supports the clocks, resets=
 and
> +  power domains on SC8280xp.
> +
> +  See also:
> +  - dt-bindings/clock/qcom,gcc-sc8280xp.h
> +
> +properties:
> +  compatible:
> +    const: qcom,gcc-sc8280xp
> +
> +  clocks:
> +    items:
> +      - description: XO reference clock

"clock" is redundant in all these descriptions. Please remove.

> +      - description: Sleep clock
> +      - description: UFS memory first RX symbol clock
> +      - description: UFS memory second RX symbol clock
> +      - description: UFS memory first TX symbol clock
> +      - description: UFS card first RX symbol clock
> +      - description: UFS card second RX symbol clock
> +      - description: UFS card first TX symbol clock
> +      - description: Primary USB SuperSpeed pipe clock
> +      - description: gcc_usb4_phy_pipegmux_clk_src
> +      - description: gcc_usb4_phy_dp_gmux_clk_src
> +      - description: gcc_usb4_phy_sys_pipegmux_clk_src
> +      - description: usb4_phy_gcc_usb4_pcie_pipe_clk
> +      - description: usb4_phy_gcc_usb4rtr_max_pipe_clk
> +      - description: Primary USB4 RX0 clock
> +      - description: Primary USB4 RX1 clock
> +      - description: Secondary USB SuperSpeed pipe clock
> +      - description: gcc_usb4_1_phy_pipegmux_clk_src
> +      - description: gcc_usb4_1_phy_dp_gmux_clk_src
> +      - description: gcc_usb4_1_phy_sys_pipegmux_clk_src
> +      - description: usb4_1_phy_gcc_usb4_pcie_pipe_clk
> +      - description: usb4_1_phy_gcc_usb4rtr_max_pipe_clk
> +      - description: Secondary USB4 RX0 clock
> +      - description: Secondary USB4 RX0 clock
> +      - description: Multiport USB first SupserSpeed pipe clock
> +      - description: Multiport USB second SuperSpeed pipe clock
> +      - description: PCIe 2a pipe clock
> +      - description: PCIe 2b pipe clock
> +      - description: PCIe 3a pipe clock
> +      - description: PCIe 3b pipe clock
> +      - description: PCIe 4 pipe clock
> +      - description: First EMAC controller reference clock
> +      - description: Second EMAC controller reference clock
> +
> +  clock-names:
> +    items:
> +      - const: bi_tcxo
> +      - const: sleep_clk

And "_clk" postfix is redundant in all these strings. Remove?

> +      - const: ufs_phy_rx_symbol_0_clk
> +      - const: ufs_phy_rx_symbol_1_clk
> +      - const: ufs_phy_tx_symbol_0_clk
> +      - const: ufs_card_rx_symbol_0_clk
> +      - const: ufs_card_rx_symbol_1_clk
> +      - const: ufs_card_tx_symbol_0_clk
> +      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
> +      - const: gcc_usb4_phy_pipegmux_clk_src
> +      - const: gcc_usb4_phy_dp_gmux_clk_src
> +      - const: gcc_usb4_phy_sys_pipegmux_clk_src
> +      - const: usb4_phy_gcc_usb4_pcie_pipe_clk
> +      - const: usb4_phy_gcc_usb4rtr_max_pipe_clk
> +      - const: qusb4phy_gcc_usb4_rx0_clk
> +      - const: qusb4phy_gcc_usb4_rx1_clk
> +      - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk