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Miller" , Jakub Kicinski , Paolo Abeni Subject: Re: [PATCH 2/2] net: dsa: mv88e6xxx: Handle single-chip-address OF property Message-ID: <20220423171857.3d731efb@thinkpad> In-Reply-To: References: <20220423131427.237160-1-nathan@nathanrossi.com> <20220423131427.237160-2-nathan@nathanrossi.com> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 24 Apr 2022 00:41:22 +1000 Nathan Rossi wrote: > On Sun, 24 Apr 2022 at 00:07, Andrew Lunn wrote: > > > > On Sat, Apr 23, 2022 at 01:14:27PM +0000, Nathan Rossi wrote: =20 > > > Handle the parsing and use of single chip addressing when the switch = has > > > the single-chip-address property defined. This allows for specifying = the > > > switch as using single chip addressing even when mdio address 0 is us= ed > > > by another device on the bus. This is a feature of some switches (e.g. > > > the MV88E6341/MV88E6141) where the switch shares the bus only respond= ing > > > to the higher 16 addresses. =20 > > > > Hi Nathan > > > > I think i'm missing something in this explanation: > > > > smi.c says: > > > > /* The switch ADDR[4:1] configuration pins define the chip SMI device a= ddress > > * (ADDR[0] is always zero, thus only even SMI addresses can be strappe= d). > > * > > * When ADDR is all zero, the chip uses Single-chip Addressing Mode, as= suming it > > * is the only device connected to the SMI master. In this mode it resp= onds to > > * all 32 possible SMI addresses, and thus maps directly the internal d= evices. > > * > > * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, all= owing > > * multiple devices to share the SMI interface. In this mode it respond= s to only > > * 2 registers, used to indirectly access the internal SMI devices. > > * > > * Some chips use a different scheme: Only the ADDR4 pin is used for > > * configuration, and the device responds to 16 of the 32 SMI > > * addresses, allowing two to coexist on the same SMI interface. > > */ > > > > So if ADDR =3D 0, it takes up the whole bus. And in this case reg =3D 0. > > If ADDR !=3D 0, it is in multi chip mode, and DT reg =3D ADDR. > > > > int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, > > struct mii_bus *bus, int sw_addr) > > { > > if (chip->info->dual_chip) > > chip->smi_ops =3D &mv88e6xxx_smi_dual_direct_ops; > > else if (sw_addr =3D=3D 0) > > chip->smi_ops =3D &mv88e6xxx_smi_direct_ops; > > else if (chip->info->multi_chip) > > chip->smi_ops =3D &mv88e6xxx_smi_indirect_ops; > > else > > return -EINVAL; > > > > This seems to implement what is above. smi_direct_ops =3D=3D whole bus, > > smi_indirect_ops =3D=3D multi-chip mode. > > > > In what situation do you see this not working? What device are you > > using, what does you DT look like, and what at the ADDR value? =20 >=20 > The device I am using is the MV88E6141, it follows the second scheme > such that it only responds to the upper 16 of the 32 SMI addresses in > single chip addressing mode. I am able to define the switch at address > 0, and everything works. However in the device I am using (Netgate > SG-3100) the ethernet phys for the non switch ethernet interfaces are > also on the same mdio bus as the switch. One of those phys is > configured with address 0. Defining both the ethernet-phy and switch > as address 0 does not work. This makes the need of new property reasonable. You can add my Acked-by: Marek Beh=C3=BAn