Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Subject: Re: [PATCH 06/12] clk: sunxi=ng: add support for R329 CCUs
To:     Icenowy Zheng <icenowy@aosc.io>
Cc:     Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Andre Przywara <andre.przywara@arm.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
        Icenowy Zheng <icenowy@aosc.io>
References: <20220422140902.1058101-1-icenowy@aosc.io>
 <BYAPR20MB2472930AAFFBDC0ACB9A7487BCF79@BYAPR20MB2472.namprd20.prod.outlook.com>
From:   Samuel Holland <samuel@sholland.org>
Message-ID: <c858b944-d72f-4e59-6a1a-329b5b8949c4@sholland.org>
Date:   Sat, 23 Apr 2022 21:12:38 -0500
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101
 Thunderbird/68.6.0
MIME-Version: 1.0
In-Reply-To: <BYAPR20MB2472930AAFFBDC0ACB9A7487BCF79@BYAPR20MB2472.namprd20.prod.outlook.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Precedence: bulk

On 4/22/22 10:41 AM, icenowy@outlook.com wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
> 
> Allwinner R329 has two CCUs, one in CPUX and another in PRCM.
> 
> Add support for them.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

There is a typo in your commit title. = should be -.

Thanks for updating the driver to use .fw_name and be loadable as a module. All
of those changes look good.

There are still some missing clocks here compared to the BSP, and a couple of
other minor issues. Please see my earlier review:

https://lore.kernel.org/linux-sunxi/99a74950-fdc0-ecfe-e5f0-ba4a7d8751f0@sholland.org/

So far it's been consistent that any settable bits in the CCU registers actually
do something. So I would expect all of those bits to have an index reserved in
the binding, even if we do not model them. I want to avoid having to go back and
add gates to the binding out-of-order later, like we are doing for H6.

Regards,
Samuel