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Date:   Sat, 23 Apr 2022 17:27:21 +0300
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Subject: Re: [PATCH V2 2/8] dt-bindings: PCI: tegra: Add device tree support
 for Tegra234
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To:     Vidya Sagar <vidyas@nvidia.com>, bhelgaas@google.com,
        lorenzo.pieralisi@arm.com, robh+dt@kernel.org,
        thierry.reding@gmail.com, jonathanh@nvidia.com
Cc:     kishon@ti.com, vkoul@kernel.org, kw@linux.com, krzk@kernel.org,
        p.zabel@pengutronix.de, mperttunen@nvidia.com,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
        linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-phy@lists.infradead.org, kthota@nvidia.com,
        mmaddireddy@nvidia.com, sagar.tv@gmail.com
References: <20220423124858.25946-1-vidyas@nvidia.com>
 <20220423124858.25946-3-vidyas@nvidia.com>
From:   Raul Tambre <raul@tambre.ee>
In-Reply-To: <20220423124858.25946-3-vidyas@nvidia.com>
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On 2022-04-23 15:48, Vidya Sagar wrote:
> @@ -47,16 +64,33 @@ Required properties:
>     "p2u-N": where N ranges from 0 to one less than the total number of lanes
>   - nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
>     by controller-id. Following are the controller ids for each controller.
> +  Tegra194:
> +  ---------
>       0: C0
>       1: C1
>       2: C2
>       3: C3
>       4: C4
>       5: C5
> +  Tegra194:

Should this be Tegra234?

> +  ---------
> +    0 : C0
> +    1 : C1
> +    2 : C2
> +    3 : C3
> +    4 : C4
> +    5 : C5
> +    6 : C6
> +    7 : C7
> +    8 : C8
> +    9 : C9
> +    10: C10