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Date:   Mon, 25 Apr 2022 20:14:07 +0200
From:   Sebastian Reichel <sebastian.reichel@collabora.com>
To:     Robin Murphy <robin.murphy@arm.com>
Cc:     Heiko Stuebner <heiko@sntech.de>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, linux-clk@vger.kernel.org,
        linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, kernel@lists.collabora.co.uk,
        Kever Yang <kever.yang@rock-chips.com>, kernel@collabora.com,
        Yifeng Zhao <yifeng.zhao@rock-chips.com>,
        Elaine Zhang <zhangqing@rock-chips.com>,
        Sugar Zhang <sugar.zhang@rock-chips.com>
Subject: Re: [PATCHv1 18/19] arm64: dts: rockchip: Add base DT for rk3588 SoC
Message-ID: <20220425181407.lknemxqooz7yidcz@mercury.elektranox.org>
References: <20220422170920.401914-1-sebastian.reichel@collabora.com>
 <20220422170920.401914-19-sebastian.reichel@collabora.com>
 <36551341-60f5-8b61-59d1-176ece8204d6@arm.com>
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Hi,

Thanks for having a look.

On Fri, Apr 22, 2022 at 07:16:13PM +0100, Robin Murphy wrote:
> On 2022-04-22 18:09, Sebastian Reichel wrote:
> > ...
> > +		cpu_l0: cpu@0 {
> > +			device_type =3D "cpu";
> > +			compatible =3D "arm,cortex-a55";
> > +			reg =3D <0x0>;
> > +			enable-method =3D "psci";
> > +			capacity-dmips-mhz =3D <530>;
> > +			clocks =3D <&scmi_clk SCMI_CLK_CPUL>;
> > +			i-cache-size =3D <32768>;
> > +			i-cache-line-size =3D <64>;
> > +			i-cache-sets =3D <128>;
> > +			d-cache-size =3D <32768>;
> > +			d-cache-line-size =3D <64>;
> > +			d-cache-sets =3D <128>;
> > +			next-level-cache =3D <&l2_cache_l0>;
> > +			#cooling-cells =3D <2>;
> > +			dynamic-power-coefficient =3D <228>;
> > +		};
>=20
> Is there any particular reason for not including more of the CPUs?

Yes, see below.

> > +		its: interrupt-controller@fe640000 {
> > +			compatible =3D "arm,gic-v3-its";
> > +			msi-controller;
> > +			#msi-cells =3D <1>;
> > +			reg =3D <0x0 0xfe640000 0x0 0x20000>;
> > +		};
> > +	};
>=20
> Does the ITS (and other bits related to GIC memory accesses) actually wor=
k,
> or will we have more of the same issues as RK356x?

The GIC in RK3588 is has the same shareability limitation as the RK356x,
but fixed the 32bit limitation. That's why I just added the boot cpu core
for now; adding any other cpu core breaks the boot without the downstream
shareability patch and I'm still investigating.

-- Sebastian

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