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From:   Peter Geis <pgwipeout@gmail.com>
Date:   Mon, 25 Apr 2022 15:37:41 -0400
Message-ID: <CAMdYzYr4ZNDzLGn-ArT4dW+F5c598rsWpACNMpuJRMY7a0yb=A@mail.gmail.com>
Subject: Re: [PATCHv1 18/19] arm64: dts: rockchip: Add base DT for rk3588 SoC
To:     Sebastian Reichel <sebastian.reichel@collabora.com>
Cc:     Robin Murphy <robin.murphy@arm.com>,
        Heiko Stuebner <heiko@sntech.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, linux-clk@vger.kernel.org,
        linux-mmc@vger.kernel.org,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
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        kernel@lists.collabora.co.uk,
        Kever Yang <kever.yang@rock-chips.com>, kernel@collabora.com,
        Yifeng Zhao <yifeng.zhao@rock-chips.com>,
        Elaine Zhang <zhangqing@rock-chips.com>,
        Sugar Zhang <sugar.zhang@rock-chips.com>
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On Mon, Apr 25, 2022 at 2:14 PM Sebastian Reichel
<sebastian.reichel@collabora.com> wrote:
>
> Hi,
>
> Thanks for having a look.
>
> On Fri, Apr 22, 2022 at 07:16:13PM +0100, Robin Murphy wrote:
> > On 2022-04-22 18:09, Sebastian Reichel wrote:
> > > ...
> > > +           cpu_l0: cpu@0 {
> > > +                   device_type = "cpu";
> > > +                   compatible = "arm,cortex-a55";
> > > +                   reg = <0x0>;
> > > +                   enable-method = "psci";
> > > +                   capacity-dmips-mhz = <530>;
> > > +                   clocks = <&scmi_clk SCMI_CLK_CPUL>;
> > > +                   i-cache-size = <32768>;
> > > +                   i-cache-line-size = <64>;
> > > +                   i-cache-sets = <128>;
> > > +                   d-cache-size = <32768>;
> > > +                   d-cache-line-size = <64>;
> > > +                   d-cache-sets = <128>;
> > > +                   next-level-cache = <&l2_cache_l0>;
> > > +                   #cooling-cells = <2>;
> > > +                   dynamic-power-coefficient = <228>;
> > > +           };
> >
> > Is there any particular reason for not including more of the CPUs?
>
> Yes, see below.
>
> > > +           its: interrupt-controller@fe640000 {
> > > +                   compatible = "arm,gic-v3-its";
> > > +                   msi-controller;
> > > +                   #msi-cells = <1>;
> > > +                   reg = <0x0 0xfe640000 0x0 0x20000>;
> > > +           };
> > > +   };
> >
> > Does the ITS (and other bits related to GIC memory accesses) actually work,
> > or will we have more of the same issues as RK356x?
>
> The GIC in RK3588 is has the same shareability limitation as the RK356x,
> but fixed the 32bit limitation. That's why I just added the boot cpu core
> for now; adding any other cpu core breaks the boot without the downstream
> shareability patch and I'm still investigating.

There's no way to avoid this issue unfortunately.
See my awful hacked together patch:
https://gitlab.com/pine64-org/quartz-bsp/linux-next/-/commit/8b34fd2a74321f8f5d7731b63eee0f9e03d1393b

Considering the ITS exists pretty much just for MSIs, and my PCIe
series introduces support for legacy interrupts, you may get away with
doing the mbi-alias currently implemented in rk356x.
Note, there are *some* compatibility issues with mbi-alias MSIs,
particularly with high IRQ cards like the Intel x520.

>
> -- Sebastian
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