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Date:   Mon, 25 Apr 2022 23:05:12 +0200
From:   Jonathan =?utf-8?Q?Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
To:     Linus Walleij <linus.walleij@linaro.org>
Cc:     Arnd Bergmann <arnd@arndb.de>,
        "Verdun, Jean-Marie" <verdun@hpe.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Joel Stanley <joel@jms.id.au>,
        "Hawkins, Nick" <nick.hawkins@hpe.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        OpenBMC Maillist <openbmc@lists.ozlabs.org>
Subject: Re: [PATCH v5 04/11] clocksource/drivers: Add HPE GXP timer
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On Mon, Apr 25, 2022 at 10:38:08PM +0200, Linus Walleij wrote:
> On Fri, Apr 22, 2022 at 3:16 PM Arnd Bergmann <arnd@arndb.de> wrote:
[...]
> The ixp4xx driver looks like that because the register range used for
> the timer and the watchdog is combined, i.e. it is a single IP block:
>=20
>                 timer@c8005000 {
>                         compatible =3D "intel,ixp4xx-timer";
>                         reg =3D <0xc8005000 0x100>;
>                         interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>=20
> Device tree probing does not allow two devices to probe from the same
> DT node, so this was solved by letting the (less important) watchdog
> be spawn as a platform device from the timer.
>=20
> I don't know if double-probing for the same register range can be fixed,
> but I was assuming that the one-compatible-to-one-driver assumption
> was pretty hard-coded into the abstractions. Maybe it isn't?
>=20
> Another way is of course to introduce an MFD. That becomes
> problematic in another way: MFD abstractions are supposed to
> be inbetween the resource and the devices it spawns, and with
> timers/clocksources this creates a horrible special-casing since the
> MFD bus (the parent may be providing e.g. an MMIO regmap)
> then need to be early-populated and searched by the timer core
> from TIMER_OF_DECLARE() early in boot.
>=20
> So this solution was the lesser evil that I could think about.

Nuvoton NPCM platforms use yet another approach:

	timer0: timer@8000 {
		compatible =3D "nuvoton,npcm750-timer";
		interrupts =3D <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		reg =3D <0x8000 0x1C>;
		clocks =3D <&clk NPCM7XX_CLK_TIMER>;
	};

	watchdog0: watchdog@801C {
		compatible =3D "nuvoton,npcm750-wdt";
		interrupts =3D <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		reg =3D <0x801C 0x4>;
		status =3D "disabled";
		clocks =3D <&clk NPCM7XX_CLK_TIMER>;
	};


The watchdog control register is in the same register block, but
represented by a separate DT node.

(not necessarily a recommendation, but it is another existing approach.)


Jonathan

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