Received: by 2002:a05:6602:2086:0:0:0:0 with SMTP id a6csp3699301ioa; Tue, 26 Apr 2022 08:30:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyYUnC2pgx0domwbbupGPVorSj6tE34rmgvA7ym6p9EqJ5irNXg0hQz3mYS1bWAJ/OgeaY X-Received: by 2002:aa7:ce87:0:b0:425:d88c:bc92 with SMTP id y7-20020aa7ce87000000b00425d88cbc92mr15674114edv.147.1650987005410; Tue, 26 Apr 2022 08:30:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650987005; cv=none; d=google.com; s=arc-20160816; b=zL+xV0Uvf5O5W+q5voD8ZKmFGMdZsvVbtDF/+tKDqFTA0+2bVR4pVNX6aXGPVBO3y8 kd2/ps6gA4ZDB08mqh0zgttcAFXXiAXktFugxYSXwdKtQnP4wB3iEHTvIGpD6ASFqJl6 DMHtKHIPkH6phfj81y+X5L/NxjyT46yfnsnUsTLb5bR3WJxTen71ik54+4eJQ/CeSk0q b+9/ae+OXpPHZGs+78mOaGTJmQYI0f0WKBC47bDRAOY6PVtfNkWOVni45S8WDV+7U/qX aJeugERPS20HpyQ106aEusvuITG24tM3+FrMOvfNK4/ovbIcmADc0Lc/Lnnu9psRC50L qzVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=wchRf7uasp3Msv81sa2LxNNZ/QRRHIhp2gjeakQULuA=; b=sRtuYUrUQFpjefsQUTmumIKaDIpEk3hy4iYuKKuML/mbP2z22ErqB59+vYF2iSoBYS T+M3X9EzC/yZWc7YXkM3D4LPF79OuslmDMt/D1FFuwESmYh7Tt52pp3o4LXpfyJorxmy WgExhuFs6w1I/MoKkAvauT/OFOmwA4T8U6cjwTgKxSzoZlfzuZHQ6DXRl3PPJoXhFuYc B67VtNghCBtQjpyVmZ8fAxgL0nz0TURHpeeV//+Fshcg4jw6zxcV7yLPsPKYYjXflyFG 3fVbc11aI2iKcfTAe+rvhDdaNxzzCxkGxG/PurvVXPLJ9CpXRTr5oG+ox8p2R6aZOrvK wAAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=Q5AwLrqO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h13-20020a1709062dcd00b006f3a370f6bcsi3439856eji.49.2022.04.26.08.29.39; Tue, 26 Apr 2022 08:30:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=Q5AwLrqO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343927AbiDZHYr (ORCPT + 99 others); Tue, 26 Apr 2022 03:24:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343757AbiDZHYo (ORCPT ); Tue, 26 Apr 2022 03:24:44 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F41ABF18; Tue, 26 Apr 2022 00:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1650957698; x=1682493698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=wchRf7uasp3Msv81sa2LxNNZ/QRRHIhp2gjeakQULuA=; b=Q5AwLrqOx3utwQYFz5PX3dOfUoTGgYPPR93TinDaUgiS5KduPLhodPbT ZNmk2LVqlO07p3akXP5FDiQvlYNiV6ns1iqcGdkB4/yBERO1Pkm/AJpp0 KF5OEtx/X0tcDlvWmtHad4ETfuuZIX1gf8Nod+D29E47TeKz/B+ePjoWu w=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 26 Apr 2022 00:21:37 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2022 00:21:37 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 26 Apr 2022 00:21:37 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 26 Apr 2022 00:21:32 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v11 1/4] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset Date: Tue, 26 Apr 2022 12:51:03 +0530 Message-ID: <1650957666-6266-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1650957666-6266-1-git-send-email-quic_srivasam@quicinc.com> References: <1650957666-6266-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pinmux nodes for primary and secondary I2S for SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 015a347..fb1f4ca 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -359,6 +359,20 @@ bias-disable; }; +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; + &pm7325_gpios { key_vol_up_default: key-vol-up-default { pins = "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 00bacc4..0242f1d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3713,6 +3713,46 @@ function = "edp_hot"; }; + mi2s0_data0: mi2s0-data0 { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + mi2s0_data1: mi2s0-data1 { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + mi2s0_mclk: mi2s0-mclk { + pins = "gpio96"; + function = "pri_mi2s"; + }; + + mi2s0_sclk: mi2s0-sclk { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + mi2s0_ws: mi2s0-ws { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + mi2s1_data0: mi2s1-data0 { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + mi2s1_sclk: mi2s1-sclk { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + mi2s1_ws: mi2s1-ws { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; -- 2.7.4