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Date:   Wed, 27 Apr 2022 14:29:25 +0530
From:   Pratyush Yadav <p.yadav@ti.com>
To:     <Tudor.Ambarus@microchip.com>
CC:     <chentsung@chromium.org>, <michael@walle.cc>,
        <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
        <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>
Subject: Re: [RESEND PATCH] mtd: spi-nor: core: Check written SR value in
 spi_nor_write_16bit_sr_and_check()
Message-ID: <20220427085925.wlmsnr7qgi5wteod@ti.com>
References: <20220126073227.3401275-1-chentsung@chromium.org>
 <20220131171929.uk3z5sr453c3eefp@ti.com>
 <0e02112a-317c-e95b-e0d3-7ed2c74c3509@microchip.com>
 <c6b2956d-85f6-19c3-4282-23a72a1b5849@microchip.com>
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On 27/04/22 07:14AM, Tudor.Ambarus@microchip.com wrote:
> On 4/27/22 10:11, Tudor Ambarus wrote:
> > On 1/31/22 19:19, Pratyush Yadav wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On 26/01/22 03:32PM, Chen-Tsung Hsieh wrote:
> >>> Read back Status Register 1 to ensure that the written byte match the
> >>> received value and return -EIO if read back test failed.
> >>>
> >>> Without this patch, spi_nor_write_16bit_sr_and_check() only check the
> >>> second half of the 16bit. It causes errors like spi_nor_sr_unlock()
> >>> return success incorrectly when spi_nor_write_16bit_sr_and_check()
> >>> doesn't write SR successfully.
> >>>
> 
> cc to stable please

Since this has the Fixes tag, once the patch hits the MTD tree stable 
should pick it up right?

> 
> >>> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()")
> >>> Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
> >>
> >> I don't know much about this bit of code but this patch looks fine to me
> >> from the surface. Would be nice to hear from Tudor about this too since
> >> he added the function.
> > 
> > Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> >>
> >> Acked-by: Pratyush Yadav <p.yadav@ti.com>
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.