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Message-ID: <7db46c19-a92a-a13a-eb63-38e5ed31580f@intel.com>
Date:   Wed, 27 Apr 2022 15:33:30 +0300
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Subject: Re: [PATCH V1] mmc: core: Enable force hw reset
Content-Language: en-US
To:     Srinivasarao Pathipati <quic_spathi@quicinc.com>,
        ulf.hansson@linaro.org, riteshh@codeaurora.org,
        asutoshd@codeaurora.org, axboe@kernel.dk, avri.altman@wdc.com,
        kch@nvidia.com, CLoehle@hyperstone.com, swboyd@chromium.org,
        digetx@gmail.com, bigeasy@linutronix.de, linux-mmc@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Shaik Sajida Bhanu <sbhanu@codeaurora.org>,
        kamasali <quic_kamasali@quicinc.com>
References: <1650961818-13452-1-git-send-email-quic_spathi@quicinc.com>
From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
 Business Identity Code: 0357606 - 4, Domiciled in Helsinki
In-Reply-To: <1650961818-13452-1-git-send-email-quic_spathi@quicinc.com>
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On 26/04/22 11:30, Srinivasarao Pathipati wrote:
> From: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
> 
> During error recovery set need hw reset to handle
> ICE error where cqe reset is must.

How do you get ICE errors?  Doesn't it mean either the hardware
is broken or the configuration is broken?

> 
> Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
> Signed-off-by: kamasali <quic_kamasali@quicinc.com>
> Signed-off-by: Srinivasarao Pathipati <quic_spathi@quicinc.com>
> ---
>  drivers/mmc/core/block.c      | 8 +++++---
>  drivers/mmc/host/cqhci-core.c | 7 +++++--
>  include/linux/mmc/host.h      | 1 +
>  3 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c
> index b35e7a9..f63bf33 100644
> --- a/drivers/mmc/core/block.c
> +++ b/drivers/mmc/core/block.c
> @@ -1482,10 +1482,12 @@ void mmc_blk_cqe_recovery(struct mmc_queue *mq)
>  	pr_debug("%s: CQE recovery start\n", mmc_hostname(host));
>  
>  	err = mmc_cqe_recovery(host);
> -	if (err)
> +	if (err || host->need_hw_reset) {
>  		mmc_blk_reset(mq->blkdata, host, MMC_BLK_CQE_RECOVERY);
> -	else
> -		mmc_blk_reset_success(mq->blkdata, MMC_BLK_CQE_RECOVERY);
> +		if (host->need_hw_reset)
> +			host->need_hw_reset = false;
> +	}
> +	mmc_blk_reset_success(mq->blkdata, MMC_BLK_CQE_RECOVERY);
>  
>  	pr_debug("%s: CQE recovery done\n", mmc_hostname(host));
>  }
> diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c
> index b0d30c3..311b510 100644
> --- a/drivers/mmc/host/cqhci-core.c
> +++ b/drivers/mmc/host/cqhci-core.c
> @@ -812,18 +812,21 @@ static void cqhci_finish_mrq(struct mmc_host *mmc, unsigned int tag)
>  irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
>  		      int data_error)
>  {
> -	u32 status;
> +	u32 status, ice_err;
>  	unsigned long tag = 0, comp_status;
>  	struct cqhci_host *cq_host = mmc->cqe_private;
>  
>  	status = cqhci_readl(cq_host, CQHCI_IS);
>  	cqhci_writel(cq_host, status, CQHCI_IS);
> +	ice_err = status & (CQHCI_IS_GCE | CQHCI_IS_ICCE);
>  
>  	pr_debug("%s: cqhci: IRQ status: 0x%08x\n", mmc_hostname(mmc), status);
>  
>  	if ((status & (CQHCI_IS_RED | CQHCI_IS_GCE | CQHCI_IS_ICCE)) ||
> -	    cmd_error || data_error)
> +	    cmd_error || data_error || ice_err){
> +		mmc->need_hw_reset = true;
>  		cqhci_error_irq(mmc, status, cmd_error, data_error);
> +	}
>  
>  	if (status & CQHCI_IS_TCC) {
>  		/* read TCN and complete the request */
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index c193c50..3d00bcf 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -492,6 +492,7 @@ struct mmc_host {
>  	int			cqe_qdepth;
>  	bool			cqe_enabled;
>  	bool			cqe_on;
> +	bool                    need_hw_reset;
>  
>  	/* Inline encryption support */
>  #ifdef CONFIG_MMC_CRYPTO