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[23.128.96.19]) by mx.google.com with ESMTPS id j65-20020a638b44000000b003aaf7a4e992si1740151pge.111.2022.04.27.08.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 08:17:50 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=FBx4GZjh; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E610A3E0F3; Wed, 27 Apr 2022 07:48:56 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238751AbiD0Ovt (ORCPT + 99 others); Wed, 27 Apr 2022 10:51:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238750AbiD0Ouj (ORCPT ); Wed, 27 Apr 2022 10:50:39 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 357A03BA4B; Wed, 27 Apr 2022 07:47:27 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23R8jpdZ029645; Wed, 27 Apr 2022 07:47:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=IXW8izC+70e6HnGnlIiBj31HZtDnovvL6iYq2sB8/5A=; b=FBx4GZjhRGy/Dq5FDKGVUM/eS4zyXQGcfuHJuVwK8xjTUWFSsuBrfzbZysXQLDB2u3m6 GMArQqb6hSBSptrFIY8qWRhl70vB/hWEFmaUCUfAtlWoCXcbQJm+xuY6LmCYnLTwt37H 8qpNniETqBAvRLZSbOYIAbsF8l57HjSilLWg4Butold3AC+qArIALoH97yQdDpAX2550 EMAKffIs4Fgfc9kmB7PJC1Gy8IUmr1xvDq6Sbr8qwAnQX3OFLYZz2Wb1EdknvyL85vSC tHgSeRB3vwI8CEA9QdO85Po0tA3wt3J87RkjgYSA5hyAWgtJUk558KQuoJ8BtLehHfvT DA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fprsqu7c4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Apr 2022 07:47:24 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 07:47:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 07:47:23 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 2EB883F7063; Wed, 27 Apr 2022 07:47:23 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , , , , , Piyush Malgujar Subject: [PATCH 4/5] gpio: thunderx: extend PIN_SEL_MASK to cover otx2 platform Date: Wed, 27 Apr 2022 07:46:19 -0700 Message-ID: <20220427144620.9105-5-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220427144620.9105-1-pmalgujar@marvell.com> References: <20220427144620.9105-1-pmalgujar@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: wZSqUzC7mEqMcS_b2O2sMGq8zt872j0H X-Proofpoint-GUID: wZSqUzC7mEqMcS_b2O2sMGq8zt872j0H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-27_04,2022-04-27_01,2022-02-23_01 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Extending the PIN_SEL_MASK to support otx2 platform which was earlier RAZ. Signed-off-by: Piyush Malgujar --- drivers/gpio/gpio-thunderx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index 451c412512450fea717937376002d2ba35d1c508..87ab1ad7e652347a67b7747ea497b944498a8b41 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -32,7 +32,7 @@ #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4 #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8 #define GPIO_BIT_CFG_TX_OD BIT(12) -#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16) +#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(26, 16) #define GPIO_INTR 0x800 #define GPIO_INTR_INTR BIT(0) #define GPIO_INTR_INTR_W1S BIT(1) -- 2.17.1