Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp211975iob; Thu, 28 Apr 2022 00:11:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkjyJOhq9NwwOD/Rl1kHtGft792ufVWOswbLS3r7FKPVGgPzy4RwHoM0g1XCd+r+/0QBfV X-Received: by 2002:a50:bae7:0:b0:425:c0fa:e0a7 with SMTP id x94-20020a50bae7000000b00425c0fae0a7mr32297145ede.104.1651129877272; Thu, 28 Apr 2022 00:11:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651129877; cv=none; d=google.com; s=arc-20160816; b=sAaDoxKyxYizjHpILNvuxHfJPb3zg5KXdK7JNe6CY56HTqSWrXKpcAmMMYIK5GiIaG RJytC/AxAKmxQ9NoJfoTUEP2IzC7DiELeN7RSwU1nU32qTdcCnP7oYXsP+ndHilZbI78 LRqVNcW028GqhyIQ53qdusmsF4Ov6L2Gh0ENCAX69HiH1resCJ1m373wKdINOI3nVXUY q190B4cq8jN4WMo52Riu8Wio9xdcnyOUciD4e3LHIunAFNc3/oFPAJboXRHLvnbBMh3C j8zaocihio+t78XYfEDy9fthMw/PuH+97W4DkSqSv9gGvLYnP+znflCZvbFUrEPHnj7T 9khQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OhR72xqFkzDx/cOjDRLsolT9JZibeLMb3xt2MB4DjB8=; b=W9RQBEOLsF4Ws6DN1U4rJnG6EFSiiWVRNMdowxbddGL7e/9PcAAkuA6o43BrSZ/Mu0 j7enr7uBftLsVL13ffSKXTRXAiTM6rjqOXPqvOx1Ua2E0B6lSVlEPj4Kzt15RrVAvwMZ cd1w7Mc+iN6qN7HQiAK0gSd+vf4Gf8VjA3h7/mLgwBqMYAtmC60pIOjT87eGVhoK6RG6 Olauv9o456lLLU6glN0JYiVw1WfWLGt5T7/4XE2NjNmidZGyXGfx4ZOb8cNUqgIPDQ2K yOC/MrTlvjuAaX3vDkxKhCpMI4Jxufle3BTY+fA3tOOKLYImQRucF3HBn50iC/GKBz7+ JLlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=qBsYb38Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e21-20020a50ec95000000b00425fcc5d236si3299283edr.53.2022.04.28.00.10.52; Thu, 28 Apr 2022 00:11:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=qBsYb38Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240345AbiD1BQ0 (ORCPT + 99 others); Wed, 27 Apr 2022 21:16:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231307AbiD1BQW (ORCPT ); Wed, 27 Apr 2022 21:16:22 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D88D7DA98; Wed, 27 Apr 2022 18:13:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651108389; x=1682644389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=OhR72xqFkzDx/cOjDRLsolT9JZibeLMb3xt2MB4DjB8=; b=qBsYb38QPJ3aPG9e2ozQPwGaRMKkiT6aV2KTGGYHtbV1pODu3byBQ+FV Fryg9AY0T0kwZh23cisBcxOcB/xMOqo+fX0whlhCitgMUqR0vvE4zAjns Ktnvgze3J6z97MarXic9anLD9fgiYrZRPJbrSjaW6chF838O1gh/c078p E=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Apr 2022 18:13:09 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 18:13:09 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 18:13:08 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 18:13:05 -0700 From: Fenglin Wu To: , , , Greg Kroah-Hartman , "Kiran Gunda" , Abhijeet Dharmapurikar CC: , , , , , Subbaraman Narayanamurthy , David Collins Subject: [RESEND PATCH V6 03/10] spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq Date: Thu, 28 Apr 2022 09:12:42 +0800 Message-ID: <1651108369-11059-4-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651108369-11059-1-git-send-email-quic_fenglinw@quicinc.com> References: <1651108369-11059-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Subbaraman Narayanamurthy Currently, cleanup_irq() is invoked when a peripheral's interrupt fires and there is no mapping present in the interrupt domain of spmi interrupt controller. The cleanup_irq clears the arbiter bit, clears the pmic interrupt and disables it at the pmic in that order. The last disable in cleanup_irq races with request_irq() in that it stomps over the enable issued by request_irq. Fix this by not writing to the pmic in cleanup_irq. The latched bit will be left set in the pmic, which will not send us more interrupts even if the enable bit stays enabled. When a client wants to request an interrupt, use the activate callback on the irq_domain to clear latched bit. This ensures that the latched, if set due to the above changes in cleanup_irq or when the bootloader leaves it set, gets cleaned up, paving way for upcoming interrupts to trigger. With this, there is a possibility of unwanted triggering of interrupt right after the latched bit is cleared - the interrupt may be left enabled too. To avoid that, clear the enable first followed by clearing the latched bit in the activate callback. Fixes: 6bc546e71e50 ("spmi: pmic-arb: cleanup unrequested irqs") Fixes: 02abec3616c1 ("spmi: pmic-arb: rename pa_xx to pmic_arb_xx and other cleanup") Signed-off-by: Subbaraman Narayanamurthy [collinsd@codeaurora.org: fix merge conflict] Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 719bd73..2bc3b88 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -593,16 +593,6 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); } static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) @@ -780,6 +770,7 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, u16 apid = hwirq_to_apid(d->hwirq); u16 sid = hwirq_to_sid(d->hwirq); u16 irq = hwirq_to_irq(d->hwirq); + u8 buf; if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", @@ -788,6 +779,10 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, return -ENODEV; } + buf = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); + return 0; } -- 2.7.4