Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp391102iob; Thu, 28 Apr 2022 04:57:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyqYqWP+nbyfGjJoCvzM/185YBBg+ygITQgVYrJ2ipJYhn90GJMp3JVwlk9MnXzPfTO56/x X-Received: by 2002:a17:906:54c3:b0:6ef:d07b:c8ec with SMTP id c3-20020a17090654c300b006efd07bc8ecmr30920797ejp.687.1651147050383; Thu, 28 Apr 2022 04:57:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651147050; cv=none; d=google.com; s=arc-20160816; b=s3mn4d4pIgWpQVpUDt0Fjh57ofujC5/02TWh53S+BjXqZPgTofSasIIpX15ZhTSvGC zZSDx5eY2XBPb1dUO2glxLb1ATi06CExCTXd+CXgWNU8/qOX3SgujqtFfc+Y307vlNIh qkzmdHAo9EckQ3b2207M948HWVfhVzo1d3KOarWcmDZUJuBZmfV3lQMXmGM89ACLKU/r r7zJSqRbgxVTxn97wPyqwa10kuMQS0f2Z9bvEkC7lG6sM2WvBFK7bH8q2pECg/+clIWp z5Dw750eYp4xPxxpcLC0f+aNNWPlfER3nAuWLBUXc/raBPenNofdf7+5IVdjb9RfYHLh 3mLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id:dkim-signature; bh=OzLHedGGs0p8Rkynak6Kv3mvYKpyq/SCmi4nw9hwu+U=; b=tooahVJQ78NszNkMzham6rLlGjJJDVftrIm9DeaJy2JJ/OuTGmXqy/hdRTLuWYiCIm Fy9bp6RNnk54CIXp3eWJdCC1vRU+kgRrnOQcqTddMbUB0k+01kfaR8ihuPFeWdWnigtE nur02ZU4GR7hbJp56q6TmhTYyBGwPgIv2cBt+n/6U+vDleZ7fi7wb/UaF+MUvx8tVkpM Fs+rMf2Rh1N/Tv/oSK9A0/+pGU9kb7ZmqF+na6jrraOYbwXojQ5mY9WMa8xQISFlDe6L CF34Db+ODzC/4vK8yONUpJ1vAVKmF3rRq7sX1NY8109venvWiLWpA86eofWq7B2aUTPt 5VsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=ayglFXAD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z6-20020a50e686000000b00425e4f457d2si4118098edm.394.2022.04.28.04.57.05; Thu, 28 Apr 2022 04:57:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=ayglFXAD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241683AbiD1DTm (ORCPT + 99 others); Wed, 27 Apr 2022 23:19:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233318AbiD1DTi (ORCPT ); Wed, 27 Apr 2022 23:19:38 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AF03189; Wed, 27 Apr 2022 20:16:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651115784; x=1682651784; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=OzLHedGGs0p8Rkynak6Kv3mvYKpyq/SCmi4nw9hwu+U=; b=ayglFXADbyBsMoLPXTsZHxrSqDqrYrcZ0Tl/xUz8X8JkLBhalW6oxOPp RdwY8auoxX9du1CBrR4PsDt/maSjPVIg13w/F48VR7RmJEdWdcA2O3nwF qj//kpTdJeUymxPscWd28i0AJVMq+9mMK+ZJKFo6/psEnUT4mqB72B2xb E=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 27 Apr 2022 20:16:23 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:16:23 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 20:16:23 -0700 Received: from [10.50.42.7] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 20:16:19 -0700 Message-ID: <2cb26bc2-704b-86df-15ed-8c18f81addaf@quicinc.com> Date: Thu, 28 Apr 2022 08:46:15 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCHv10 5/6] lib: Add register read/write tracing support Content-Language: en-US To: Arnd Bergmann CC: Will Deacon , Catalin Marinas , Steven Rostedt , Marc Zyngier , "Trilok Soni" , , gregkh , Linux ARM , Linux Kernel Mailing List , linux-arm-msm , Prasad Sodagudi References: <8cf9304d9941c25d920c4835cbc624ff5c2ac2cb.1644824638.git.quic_saipraka@quicinc.com> From: Sai Prakash Ranjan In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Arnd, On 4/27/2022 9:44 PM, Arnd Bergmann wrote: > On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan > wrote: >> From: Prasad Sodagudi >> >> Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors >> are typically used to read/write from/to memory mapped registers >> and can cause hangs or some undefined behaviour in following few >> cases, >> >> * If the access to the register space is unclocked, for example: if >> there is an access to multimedia(MM) block registers without MM >> clocks. >> >> * If the register space is protected and not set to be accessible from >> non-secure world, for example: only EL3 (EL: Exception level) access >> is allowed and any EL2/EL1 access is forbidden. >> >> * If xPU(memory/register protection units) is controlling access to >> certain memory/register space for specific clients. >> >> and more... >> >> Such cases usually results in instant reboot/SErrors/NOC or interconnect >> hangs and tracing these register accesses can be very helpful to debug >> such issues during initial development stages and also in later stages. >> >> So use ftrace trace events to log such MMIO register accesses which >> provides rich feature set such as early enablement of trace events, >> filtering capability, dumping ftrace logs on console and many more. >> >> Sample output: >> >> rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700 >> rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700 >> rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610 >> rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610 >> >> Signed-off-by: Prasad Sodagudi >> Co-developed-by: Sai Prakash Ranjan >> Signed-off-by: Sai Prakash Ranjan > I think this is ok in general. I saw that Steve had a minor comment, and > I suppose you could have just resent the same patches with a fixup in order > to have me pick it up into the asm-generic tree for 5.19. I had it ready the same day Steve gave the comment :) but given there was no further reviews on other patches, I thought of slowing down the posting of new versions. I will send v11 now. > There is one more thing that I saw looking through this patch again: the > address you print is the virtual __iomem token, but it might be more > valuable to have the physical address instead, which can be looked up > in the devicetree to know which register is affected. > > There is a small extra cost to walk the page table, and I'm not sure > if we actually have an interface for it (vmalloc_to_page is almost > what we want, but it returns an invalid page pointer). Any suggestions > on this? > > Right, it would be useful but currently we rely on the caller information (the function name and the offset) to identify who writes to the location and then post process to identify the register written based on it. I am also not aware of the interface for page table walk and the walk on this hot trace path (note that we are capturing every register read/write) would slow down the system further. Even in the internal versions, we get the physical address postmortem from the parser tool [1]. [1] https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/linux-ramdump-parser-v2/parsers/rtb.py#n72 Given that we can add fields to this tracepoint without breaking ABI, we can probably add this addon at a later point. Thanks, Sai