Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Fri, 29 Apr 2022 15:05:24 +0200
From:   Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>
To:     Andrew Lunn <andrew@lunn.ch>
Cc:     Gregory Clement <gregory.clement@bootlin.com>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] irqchip/armada-370-xp: Do not touch Performance
 Counter Overflow on A375, A38x, A39x
Message-ID: <20220429130524.vs6mlzvotvaortbw@pali>
References: <20220425113706.29310-1-pali@kernel.org>
 <YmvYrFUfIUvfjrmY@lunn.ch>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <YmvYrFUfIUvfjrmY@lunn.ch>
User-Agent: NeoMutt/20180716
Precedence: bulk

On Friday 29 April 2022 14:23:08 Andrew Lunn wrote:
> On Mon, Apr 25, 2022 at 01:37:05PM +0200, Pali Rohár wrote:
> > Register ARMADA_370_XP_INT_FABRIC_MASK_OFFS is Armada 370 and XP specific
> > and on new Armada platforms it has different meaning. It does not configure
> > Performance Counter Overflow interrupt masking. So do not touch this
> > register on non-A370/XP platforms (A375, A38x and A39x).
> 
> Hi Pali
> 
> Do the Armada 375, 38x and 39x have an over flow interrupt? I assume
> not.

Hello! According to documentation there is something named performance
counter interrupt, but it is in different register... and this register
is not per-cpu.

> Does this need a fixes tag? Should it be back ported in stable?

git blame show that this functionality appeared in commit 28da06dfd9e4
("irqchip: armada-370-xp: Enable the PMU interrupts").