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Date:   Sat, 30 Apr 2022 00:23:34 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Pali =?iso-8859-1?Q?Roh=E1r?= <pali@kernel.org>
Cc:     Gregory Clement <gregory.clement@bootlin.com>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] irqchip/armada-370-xp: Do not touch Performance
 Counter Overflow on A375, A38x, A39x
Message-ID: <YmxlZncjVnym4kfc@lunn.ch>
References: <20220425113706.29310-1-pali@kernel.org>
 <YmvYrFUfIUvfjrmY@lunn.ch>
 <20220429130524.vs6mlzvotvaortbw@pali>
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On Fri, Apr 29, 2022 at 03:05:24PM +0200, Pali Rohár wrote:
> On Friday 29 April 2022 14:23:08 Andrew Lunn wrote:
> > On Mon, Apr 25, 2022 at 01:37:05PM +0200, Pali Rohár wrote:
> > > Register ARMADA_370_XP_INT_FABRIC_MASK_OFFS is Armada 370 and XP specific
> > > and on new Armada platforms it has different meaning. It does not configure
> > > Performance Counter Overflow interrupt masking. So do not touch this
> > > register on non-A370/XP platforms (A375, A38x and A39x).
> > 
> > Hi Pali
> > 
> > Do the Armada 375, 38x and 39x have an over flow interrupt? I assume
> > not.
> 
> Hello! According to documentation there is something named performance
> counter interrupt, but it is in different register... and this register
> is not per-cpu.

O.K, not something which can be quickly added. 

> > Does this need a fixes tag? Should it be back ported in stable?
> 
> git blame show that this functionality appeared in commit 28da06dfd9e4
> ("irqchip: armada-370-xp: Enable the PMU interrupts").

It is more a question of:

 o It must fix a real bug that bothers people (not a, “This could be a
   problem…” type thing).

From https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html

Have you seen bad things happen because of this?

     Andrew