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From:   David Laight <David.Laight@ACULAB.COM>
To:     "'Maciej W. Rozycki'" <macro@orcam.me.uk>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
CC:     "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: RE: [PATCH] MIPS: Fix CP0 counter erratum detection for R4k CPUs
Thread-Topic: [PATCH] MIPS: Fix CP0 counter erratum detection for R4k CPUs
Thread-Index: AQHYW7e8izRkWzTXwESA/9rrqnvRW60HAA6w
Date:   Fri, 29 Apr 2022 15:24:48 +0000
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 <alpine.DEB.2.21.2204291119040.9383@angie.orcam.me.uk>
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>  That said reading from the 8254 is messy too and you may need a spinlock
> (you need to write the Counter Latch or Read-Back command to the control
> register and then issue consecutive two reads to the requested timer's
> data register[2]).  Which is I guess why support for it has been removed
> from x86 code.  For non-SMP it might be good enough.

It is important to 'latch' the counter before reading it.
I tried to optimise some code to avoid the extra accesses.
In principle it ought to have worked, but reading the
unlatched values gave garbage - not just messed up 16bit values.
It was probably returning a value that was being ripple-counted.

The sheer number of IO cycles you need to read the counters
just beggars belief.
So while they can be used to get an accurate timestamp it
really takes too long to be useful.
Even in a modern x86 chipset I think they are still ISA
speed cycles.
(Mind you, we've an fpga based PCIe boards where reads
are ISA speed....)

OTOH I'd have though that for a real 486 (one without a TSC)
that is the only way to get a high res timer count.

	David

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