Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp202445iob; Mon, 2 May 2022 17:05:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHwhuLb9h3kBS/GfRk9iy3TJWoqhEoodI/oqrs1Zn2WPRdr7TZ28EMmXn443H9FZ3Mukvx X-Received: by 2002:a17:902:e051:b0:15c:e5dd:c1c0 with SMTP id x17-20020a170902e05100b0015ce5ddc1c0mr14094566plx.1.1651536343282; Mon, 02 May 2022 17:05:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651536343; cv=none; d=google.com; s=arc-20160816; b=HPECanUovTVSE4qJhDMKvgEiEkxXBe5ihWECzZPTZhJG/Uc8mscxYWzRHd8k5GMUoM mTw72rEQxRo9zFA5CRaxCsVw1861VZmnkGxeGeIIZQhhw5W6v/HEVQBciqM9Q27bVZoY WoG8xVQYRIBDH7gL+Oh1KC9zjnBK8n/jAzYONqzwF/OY1aJfJbVajhLBhRINDxeyvofz qmIvuYTtnCFXQ+D5kJcJQoud37Oh9rPwgR37ej6gw2HkvmSn3SwFAf7vMESPMd4IZflp 6e7DV0b+dMhrLhr0DGLTTxlugPkb/3z3BnN+C0OXeIQs/DA+WGRkMuQzKwGaTqEtKJ76 xcBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=48+rVERvNTQxNqzw5fqv4Nm35unnocBFemLJibc0Q54=; b=WfZ75Ni8866QLZUh7tAissCWtl0kTbpVBoz3a/QI7xhtPT/3n0vNb195jWD0LIuPeN YfKHLr4SqPNc+WR7sg32GRnruZw7nr2/qPlySm4HFjkI2SpbdlBuSQFdFknEwSH1Tm4i STFhDujdoHKbb5tiG3FjvpCvtAStLBaVkeoa2SUY7l2wdIl5CVv4xGMtyTVNd9ipI01W VlACOdcKScosH4BEaiNotvvRD8Fu1jbmqJlxHchfs6McwlbR/rRPVgoQ8yI8CNT+ajID ST9SqR+FgrEhssVKTHHWbiM33Uu0VFgDxtTaHizYvWHOOu0ve96IZ4cIpmpRJbygeq8f xsfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=eaDLduCH; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net. [23.128.96.19]) by mx.google.com with ESMTPS id z13-20020aa7888d000000b00505d916bf8esi15059834pfe.263.2022.05.02.17.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 May 2022 17:05:43 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=eaDLduCH; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CCC7B35251; Mon, 2 May 2022 17:05:10 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386497AbiEBRMC (ORCPT + 99 others); Mon, 2 May 2022 13:12:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349891AbiEBRL6 (ORCPT ); Mon, 2 May 2022 13:11:58 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F18682DC6; Mon, 2 May 2022 10:08:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651511309; x=1683047309; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=48+rVERvNTQxNqzw5fqv4Nm35unnocBFemLJibc0Q54=; b=eaDLduCHjl8YK3YdXBwwU/FX9Ma6+CUlAig76XPJJbezjjwNx6UzoKHV Dc+LpP268WdoK2aIv3lB5nEWmmj+7ZThA7q/lKl0XQLEtJIXpeVqFXyIm 2MrMcjfNtfMCR9f5MMpk24SLL6GLhwZ+FecsX9f/4S8iZdVZNRNEajd2O A=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 02 May 2022 10:08:29 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 10:08:28 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:28 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:24 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v3 2/4] ARM: dts: qcom: sdx65: Add QPIC NAND support Date: Mon, 2 May 2022 10:08:04 -0700 Message-ID: <1651511286-18690-3-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX65 platform. Since there is no "aon" clock in SDX65, a dummy clock is provided. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index d6a6087..a75e9f1 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -211,6 +217,22 @@ status = "disabled"; }; + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; -- 2.7.4