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[23.128.96.19]) by mx.google.com with ESMTPS id z1-20020a6552c1000000b003c25475a43bsi2240890pgp.757.2022.05.02.17.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 May 2022 17:37:30 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="W/KYE00/"; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 964A83C71E; Mon, 2 May 2022 17:29:18 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356464AbiEBBzO (ORCPT + 99 others); Sun, 1 May 2022 21:55:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230455AbiEBBzN (ORCPT ); Sun, 1 May 2022 21:55:13 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B89D417E28 for ; Sun, 1 May 2022 18:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651456305; x=1682992305; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=nBgb/6v6Rg6UR6PoLHzzUhaMGDDupSCLP2KtncAqse0=; b=W/KYE00/wid05ES16m/yLQM6Y8nac1U4Z0eo4rH8l7b4ssfedy783hKh gAlTmlohgGfMvsMasWxDj5Y/LmHpSn59CXczfLQFNC5+t2XOhxn4NIYHA 2i32WobZ15zrSbhgAnV97V8vAzndCNw2zM/nlm7aje+YEZeos7UMOgp6Q 6f2ncJqCYohYCNKZv4bkUUvPBRu3PxheqEpt9fwn9vBZUujID2dh4JK8V MMM/xEdVF3WuTUKBYMF+tokl632Ky9fT0ehheCzidNJ9NupFWSG0KzPYl NPB7B3+puEWTnXOUZ32YVJXjZQkVl+b6G/kCvw8vSOsIMm4Tc6p0IRPFw w==; X-IronPort-AV: E=McAfee;i="6400,9594,10334"; a="266958363" X-IronPort-AV: E=Sophos;i="5.91,190,1647327600"; d="scan'208";a="266958363" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2022 18:51:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,190,1647327600"; d="scan'208";a="707406440" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga001.fm.intel.com with ESMTP; 01 May 2022 18:51:41 -0700 From: Lu Baolu To: Joerg Roedel , Jason Gunthorpe , Christoph Hellwig , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker , Dave Jiang , Vinod Koul Cc: Eric Auger , Liu Yi L , Jacob jun Pan , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v5 00/12] iommu: SVA and IOPF refactoring Date: Mon, 2 May 2022 09:48:30 +0800 Message-Id: <20220502014842.991097-1-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi folks, The former part of this series refactors the IOMMU SVA code by assigning an SVA type of iommu_domain to a shared virtual address and replacing sva_bind/unbind iommu ops with attach/detach_dev_pasid domain ops. The latter part changes the existing I/O page fault handling framework from only serving SVA to a generic one. Any driver or component could handle the I/O page faults for its domain in its own way by installing an I/O page fault handler. This series has been functionally tested on an x86 machine and compile tested for other architectures. This series is also available on github: [2] https://github.com/LuBaolu/intel-iommu/commits/iommu-sva-refactoring-v5 Please review and suggest. Best regards, baolu Change log: v5: - Address review comments from Jean-Philippe Brucker. Very appreciated! - Remove redundant pci aliases check in device_group_immutable_singleton(). - Treat all buses exept PCI as static in immutable singleton check. - As the sva_bind/unbind() have already guaranteed sva domain free only after iopf_queue_flush_dev(), remove the unnecessary domain refcount. - Move domain get() out of the list iteration in iopf_handle_group(). v4: - https://lore.kernel.org/linux-iommu/20220421052121.3464100-1-baolu.lu@linux.intel.com/ - Solve the overlap with another series and make this series self-contained. - No objection to the abstraction of data structure during v3 review. Hence remove the RFC subject prefix. - Refine the immutable singleton group code according to Kevin's comments. v3: - https://lore.kernel.org/linux-iommu/20220410102443.294128-1-baolu.lu@linux.intel.com/ - Rework iommu_group_singleton_lockdown() by adding a flag to the group that positively indicates the group can never have more than one member, even after hot plug. - Abstract the data structs used for iommu sva in a separated patches to make it easier for review. - I still keep the RFC prefix in this series as above two significant changes need at least another round review to be finalized. - Several misc refinements. v2: - https://lore.kernel.org/linux-iommu/20220329053800.3049561-1-baolu.lu@linux.intel.com/ - Add sva domain life cycle management to avoid race between unbind and page fault handling. - Use a single domain for each mm. - Return a single sva handler for the same binding. - Add a new helper to meet singleton group requirement. - Rework the SVA domain allocation for arm smmu v3 driver and move the pasid_bit initialization to device probe. - Drop the patch "iommu: Handle IO page faults directly". - Add mmget_not_zero(mm) in SVA page fault handler. v1: - https://lore.kernel.org/linux-iommu/20220320064030.2936936-1-baolu.lu@linux.intel.com/ - Initial post. Dave Jiang (1): dmaengine: idxd: Separate user and kernel pasid enabling Lu Baolu (11): iommu: Add pasid_bits field in struct dev_iommu iommu: Add attach/detach_dev_pasid domain ops iommu/sva: Basic data structures for SVA iommu/vt-d: Remove SVM_FLAG_SUPERVISOR_MODE support iommu/vt-d: Add SVA domain support arm-smmu-v3/sva: Add SVA domain support iommu/sva: Use attach/detach_pasid_dev in SVA interfaces iommu: Remove SVA related callbacks from iommu ops iommu: Prepare IOMMU domain for IOPF iommu: Per-domain I/O page fault handling iommu: Rename iommu-sva-lib.{c,h} include/linux/intel-iommu.h | 5 +- include/linux/iommu.h | 100 ++++-- drivers/dma/idxd/idxd.h | 6 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 25 +- .../iommu/{iommu-sva-lib.h => iommu-sva.h} | 3 +- drivers/dma/idxd/cdev.c | 4 +- drivers/dma/idxd/init.c | 30 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 85 ++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +- drivers/iommu/intel/iommu.c | 20 +- drivers/iommu/intel/svm.c | 135 +++---- drivers/iommu/io-pgfault.c | 66 +--- drivers/iommu/iommu-sva-lib.c | 71 ---- drivers/iommu/iommu-sva.c | 328 ++++++++++++++++++ drivers/iommu/iommu.c | 189 +++++----- drivers/iommu/Makefile | 2 +- 16 files changed, 672 insertions(+), 425 deletions(-) rename drivers/iommu/{iommu-sva-lib.h => iommu-sva.h} (91%) delete mode 100644 drivers/iommu/iommu-sva-lib.c create mode 100644 drivers/iommu/iommu-sva.c -- 2.25.1