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References: <20220421221159.31729-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220421221159.31729-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
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From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Thu, 28 Apr 2022 11:42:08 +0200
Message-ID: <CAMuHMdVqk1ryzzK9-BZCMDPeyjfF1-8hMpzUoEPCcg8pJ2-ang@mail.gmail.com>
Subject: Re: [PATCH 2/2] irqchip: Add RZ/G2L IA55 Interrupt Controller driver
To:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc:     Marc Zyngier <maz@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Prabhakar <prabhakar.csengg@gmail.com>,
        Biju Das <biju.das.jz@bp.renesas.com>
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Hi Prabhakar,

On Fri, Apr 22, 2022 at 12:12 AM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add a driver for the Renesas RZ/G2L Interrupt Controller.
>
> This supports external pins being used as interrupts. It supports
> one line for NMI, 8 external pins and 32 GPIO pins (out of 123)
> to be used as IRQ lines.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -0,0 +1,447 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas RZ/G2L IRQC Driver
> + *
> + * Copyright (C) 2022 Renesas Electronics Corporation.
> + *
> + * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_address.h>
> +#include <linux/reset.h>
> +#include <linux/spinlock.h>
> +
> +#define IRQC_IRQ_START                 1
> +#define IRQC_IRQ_COUNT                 8
> +#define IRQC_TINT_START                        9

= IRQC_IRQ_START + IRQC_IRQ_COUNT

> +#define IRQC_TINT_COUNT                        32
> +#define IRQC_NUM_IRQ                   41

= IRQC_TINT_START + IRQC_TINT_COUNT

Should these be in a DT binding header file?

Combining all types into a single linear number space makes it hard
to extend the range, when reusing for an SoC that supports more
interrupt sources.

> +static void rzg2l_irq_eoi(struct irq_data *d)
> +{
> +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> +       unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
> +       u16 bit = BIT(hw_irq);

I guess you can just use u32?

> +       u32 reg;
> +
> +       reg = readl_relaxed(priv->base + ISCR);
> +       if (reg & bit)
> +               writel_relaxed(GENMASK(IRQC_IRQ_COUNT - 1, 0) & ~bit,

As writes to the unused upper bits are ignored, you can drop the
masking with GENMASK(IRQC_IRQ_COUNT - 1, 0), and be prepared for more
interrupt sources.

> +                              priv->base + ISCR);
> +}
> +
> +static void rzg2l_tint_eoi(struct irq_data *d)
> +{
> +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> +       unsigned int hw_irq = irqd_to_hwirq(d);

"irqd_to_hwirq(d) - IRQC_TINT_START", for symmetry with
rzg2l_irq_eoi()?

> +       u32 bit = BIT(hw_irq - IRQC_TINT_START);
> +       u32 reg;
> +
> +       reg = readl_relaxed(priv->base + TSCR);
> +       if (reg & bit)
> +               writel_relaxed(GENMASK(IRQC_TINT_COUNT - 1, 0) & ~bit,

Drop the masking with all-ones?

> +                              priv->base + TSCR);
> +}

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds