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References: <20220502064551.202613-1-michael.riesch@wolfvision.net>
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From:   Peter Geis <pgwipeout@gmail.com>
Date:   Mon, 2 May 2022 05:54:12 -0400
Message-ID: <CAMdYzYrChKVwuGj=VEc=T4Gez-Bs647GxaeMsdbgvU_6p3FeEg@mail.gmail.com>
Subject: Re: [PATCH v2] arm64: dts: rockchip: enable otg/drd operation of
 usb_host0_xhci in rk3568
To:     Michael Riesch <michael.riesch@wolfvision.net>
Cc:     devicetree <devicetree@vger.kernel.org>,
        arm-mail-list <linux-arm-kernel@lists.infradead.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Liang Chen <cl@rock-chips.com>,
        Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
        Frank Wunderlich <frank-w@public-files.de>
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On Mon, May 2, 2022 at 2:46 AM Michael Riesch
<michael.riesch@wolfvision.net> wrote:
>
> This USB 3.0 controller of the Rockchip RK3568 is capable of OTG/DRD
> operation. Enable it in the device tree.

I think I missed a conversation here, the xhci0 controller is the otg
port for both rk3566 and rk3568. The only difference is on rk3566 it
is a usb2 only controller, where on rk3568 it is also a usb3
controller. It was set to host only because my original phy patches
didn't support otg mode. Since then Samuel's series fixed that.

Your original patch was correct.

Always,
Peter

>
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
> v2:
>  - As pointed out by Nicolas, this is RK3568 specific. Moved change to
>    rk3568.dtsi.
>
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 5eafddf62edc..bbfe8f3d68b7 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -134,6 +134,7 @@ power-domain@RK3568_PD_PIPE {
>  };
>
>  &usb_host0_xhci {
> +       dr_mode = "otg";
>         phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
>         phy-names = "usb2-phy", "usb3-phy";
>  };
> --
> 2.30.2