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[82.27.106.168]) by smtp.gmail.com with ESMTPSA id i128-20020a1c3b86000000b003942a244ebfsm2217051wma.4.2022.05.03.11.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 11:12:48 -0700 (PDT) Date: Tue, 3 May 2022 19:12:24 +0100 From: Jean-Philippe Brucker To: Lu Baolu Cc: Joerg Roedel , Jason Gunthorpe , Christoph Hellwig , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker , Dave Jiang , Vinod Koul , Eric Auger , Liu Yi L , Jacob jun Pan , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 07/12] arm-smmu-v3/sva: Add SVA domain support Message-ID: References: <20220502014842.991097-1-baolu.lu@linux.intel.com> <20220502014842.991097-8-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220502014842.991097-8-baolu.lu@linux.intel.com> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 02, 2022 at 09:48:37AM +0800, Lu Baolu wrote: > Add support for SVA domain allocation and provide an SVA-specific > iommu_domain_ops. > > Signed-off-by: Lu Baolu > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 14 +++++++ > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 42 +++++++++++++++++++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 ++++++++++ > 3 files changed, 77 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index cd48590ada30..7631c00fdcbd 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -759,6 +759,10 @@ struct iommu_sva *arm_smmu_sva_bind(struct device *dev, struct mm_struct *mm, > void arm_smmu_sva_unbind(struct iommu_sva *handle); > u32 arm_smmu_sva_get_pasid(struct iommu_sva *handle); > void arm_smmu_sva_notifier_synchronize(void); > +int arm_smmu_sva_attach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id); > +void arm_smmu_sva_detach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id); > #else /* CONFIG_ARM_SMMU_V3_SVA */ > static inline bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) > { > @@ -804,5 +808,15 @@ static inline u32 arm_smmu_sva_get_pasid(struct iommu_sva *handle) > } > > static inline void arm_smmu_sva_notifier_synchronize(void) {} > + > +static inline int arm_smmu_sva_attach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id) > +{ > + return -ENODEV; > +} > + > +static inline void arm_smmu_sva_detach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, > + ioasid_t id) {} > #endif /* CONFIG_ARM_SMMU_V3_SVA */ > #endif /* _ARM_SMMU_V3_H */ > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > index c623dae1e115..3b843cd3ed67 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > @@ -541,3 +541,45 @@ void arm_smmu_sva_notifier_synchronize(void) > */ > mmu_notifier_synchronize(); > } > + > +int arm_smmu_sva_attach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id) > +{ > + int ret = 0; > + struct iommu_sva *handle; > + struct mm_struct *mm = iommu_sva_domain_mm(domain); > + > + if (domain->type != IOMMU_DOMAIN_SVA || !mm) We wouldn't get that far with a non-SVA domain since iommu_sva_domain_mm() would dereference a NULL pointer. Could you move it after the domain->type check, and maybe add a WARN_ON()? It could help catch issues in future API changes. > + return -EINVAL; > + > + mutex_lock(&sva_lock); > + handle = __arm_smmu_sva_bind(dev, mm); > + if (IS_ERR(handle)) > + ret = PTR_ERR(handle); > + mutex_unlock(&sva_lock); > + > + return ret; > +} > + > +void arm_smmu_sva_detach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id) > +{ > + struct arm_smmu_bond *bond = NULL, *t; > + struct mm_struct *mm = iommu_sva_domain_mm(domain); > + struct arm_smmu_master *master = dev_iommu_priv_get(dev); > + > + mutex_lock(&sva_lock); > + list_for_each_entry(t, &master->bonds, list) { > + if (t->mm == mm) { > + bond = t; > + break; > + } > + } > + > + if (!WARN_ON(!bond) && refcount_dec_and_test(&bond->refs)) { > + list_del(&bond->list); > + arm_smmu_mmu_notifier_put(bond->smmu_mn); > + kfree(bond); > + } > + mutex_unlock(&sva_lock); > +} > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index afc63fce6107..bd80de0bad98 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1995,10 +1995,31 @@ static bool arm_smmu_capable(enum iommu_cap cap) > } > } > > +static void arm_smmu_sva_domain_free(struct iommu_domain *domain) > +{ > + kfree(domain); > +} > + > +static const struct iommu_domain_ops arm_smmu_sva_domain_ops = { > + .attach_dev_pasid = arm_smmu_sva_attach_dev_pasid, > + .detach_dev_pasid = arm_smmu_sva_detach_dev_pasid, > + .free = arm_smmu_sva_domain_free, > +}; > + > static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) > { > struct arm_smmu_domain *smmu_domain; > > + if (type == IOMMU_DOMAIN_SVA) { > + struct iommu_domain *domain; > + > + domain = kzalloc(sizeof(*domain), GFP_KERNEL); > + if (domain) > + domain->ops = &arm_smmu_sva_domain_ops; > + > + return domain; > + } > + I'd prefer moving all of this to arm-smmu-v3-sva.c and just call arm_smmu_sva_domain_alloc() here Otherwise the patch looks fine. I'll rework the driver when I find some time, because we can now remove arm_smmu_bond and move smmu_mn to the SVA domain, maybe also remove sva_lock but I haven't thought it through. Thanks, Jean > if (type != IOMMU_DOMAIN_UNMANAGED && > type != IOMMU_DOMAIN_DMA && > type != IOMMU_DOMAIN_DMA_FQ && > -- > 2.25.1 >