Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp522333iob; Wed, 4 May 2022 02:01:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyHidrrYbh2+szc/630Jk56/JhsMd9AIW3nOrhp4DT2Zyb0flnNaPGJJ4DhJM9bZYi1btHs X-Received: by 2002:a17:902:bc46:b0:15c:f32f:39bf with SMTP id t6-20020a170902bc4600b0015cf32f39bfmr21789638plz.32.1651654889102; Wed, 04 May 2022 02:01:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651654889; cv=none; d=google.com; s=arc-20160816; b=JxoUIxDvCsgUep2n6iczk73jHl7aoNeAatAc+up9XSg23NWIDga76+twDj7pSolO14 W/m4RUnG/7t4bShO/yGMmKGQSUikH2shRZptJxoY6hzHsaFHacy2npWXugpDJGSsGkE1 vG7ZPq9QvX/cIIElg1Zmon6HV8jMCLAsZSZ83V0m+2NGIfdi+PzrlVoufdkv/Kd1yWEv n6eTVTV7cHoNs5RKtOB7wyL1MwyWOJtTSsltIN+RdU2U0ENGY8bPBIimqoWl5fz3wYfc Gd4U4OQ81/4gGJPbNriRG8EUPVHgZ5eYOnX03xHgL8/27nhmn9lcWM7zfRbW9iR6K8rH kXQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=6/S6VEzKvH8TW9AMi9YN/4HI8ctvdYhCP7Lpu5MwfW8=; b=M5eumcsn/jjigP4iP+VqOoaToi4nS2ze3BySt8MMqo6msWQiJDOaeenfQGAiNi0x4V k3WVY8PSwrd0zYgiSEx+mM/bI8okQbomgqqfMAEVzAz/GbnKSJIvAoz/TKWEXoURisZt oG2TZbXp81wWzoL44wRsqbEcBI8oAgqdXC2Izk86kqH0N/VupJn0ZCPyD1gwFRbyiCGM 06Rs47urNKVe4ADfRtNyoYJBU663O811+y0mBBhTj7e84cNgUjVnMZrW+lbPY7xeknt0 CcihBXPfz31f5RkskoCDBHux0emggCe6qEuD8E1o3NUu+EklPY4xw5zgEJbieS2g0yRt An/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baikalelectronics.ru header.s=mail header.b=aBNelTNj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c10-20020a170902724a00b00156aa838400si18340223pll.621.2022.05.04.02.01.13; Wed, 04 May 2022 02:01:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baikalelectronics.ru header.s=mail header.b=aBNelTNj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239608AbiECUNo (ORCPT + 99 others); Tue, 3 May 2022 16:13:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231937AbiECUNm (ORCPT ); Tue, 3 May 2022 16:13:42 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 20F72403EA; Tue, 3 May 2022 13:10:01 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 8DE3616D6; Tue, 3 May 2022 23:10:34 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 8DE3616D6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608634; bh=6/S6VEzKvH8TW9AMi9YN/4HI8ctvdYhCP7Lpu5MwfW8=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=aBNelTNji0cPnRAo2ZharhYi6S5vjqsNC2xDAFaOWlbKDNTHw8QGW7CJ6YOrGmlh5 Lk8YtQ9p9V5NaNcEoOwW/m7uZq7pwllCl0Xrg/Oknvg0b+kJHiPm7mflYE4yFH651v y5NNVbnEB3ws9G6xG7uBjlczHhNZnIQP6LoP9gd4= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:00 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Rob Herring , Krzysztof Kozlowski CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , Subject: [PATCH v2 02/23] dt-bindings: ata: ahci-platform: Detach common AHCI bindings Date: Tue, 3 May 2022 23:09:17 +0300 Message-ID: <20220503200938.18027-3-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to create a more sophisticated AHCI controller DT bindings let's divide the already available generic AHCI platform YAML schema into the platform part and a set of the common AHCI properties. The former part will be used to evaluate the AHCI DT nodes mainly compatible with the generic AHCI controller while the later schema will be used for more thorough AHCI DT nodes description. For instance such YAML schemas design will be useful for our DW AHCI SATA controller derivative with four clock sources, two reset lines, one system controller reference and specific max Rx/Tx DMA xfers size constraints. Note the phys and target-supply property requirement is preserved in the generic AHCI platform bindings because some platforms can lack of the explicitly specified PHYs or target device power regulators. Signed-off-by: Serge Semin --- Folks, I don't really see why the phys/target-supply requirement has been added to the generic AHCI DT schema in the first place. Probably just to imply some meaning for the sub-nodes definition. Anyway in one of the further patches I am adding the DW AHCI SATA controller DT bindings which won't require having these properties specified in the sub-nodes, but will describe additional port-specific properties. That's why I get to keep the constraints in the ahci-platform.yaml schema instead of moving them to the common schema. Changelog v2: - This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel. --- .../devicetree/bindings/ata/ahci-common.yaml | 117 ++++++++++++++++++ .../bindings/ata/ahci-platform.yaml | 68 +--------- 2 files changed, 123 insertions(+), 62 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/ahci-common.yaml diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Documentation/devicetree/bindings/ata/ahci-common.yaml new file mode 100644 index 000000000000..72e24b246040 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/ahci-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Serial ATA AHCI controllers + +maintainers: + - Hans de Goede + - Jens Axboe + +description: + This document defines device tree properties for a common AHCI SATA + controller implementation. It's hardware interface is supposed to + conform to the technical standard defined by Intel (see Serial ATA + Advanced Host Controller Interface specification for details). The + document doesn't constitute a DT-node binding by itself but merely + defines a set of common properties for the AHCI-compatible devices. + +select: false + +allOf: + - $ref: sata-common.yaml# + +properties: + reg: + description: + Generic AHCI registers space conforming to the Serial ATA AHCI + specification. + + reg-names: + description: CSR space IDs + + interrupts: + description: + Generic AHCI state change interrupt. Can be implemented either as a + single line attached to the controller as a set of the dedicated signals + for the global and particular port events. + + clocks: + description: + List of all the reference clocks connected to the controller. + + clock-names: + description: Reference clocks IDs + + resets: + description: + List of the reset control lines to reset the controller clock + domains. + + reset-names: + description: Reset line IDs + + power-domains: + description: + List of the power domain the AHCI controller being a part of. + + ahci-supply: + description: Power regulator for AHCI controller + + target-supply: + description: Power regulator for SATA target device + + phy-supply: + description: Power regulator for SATA PHY + + phys: + description: Reference to the SATA PHY node + maxItems: 1 + + phy-names: + maxItems: 1 + + ports-implemented: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Mask that indicates which ports the HBA supports. Useful if PI is not + programmed by the BIOS, which is true for some embedded SoC's. + maximum: 0x1f + +patternProperties: + "^sata-port@[0-9a-f]+$": + type: object + description: + It is optionally possible to describe the ports as sub-nodes so + to enable each port independently when dealing with multiple PHYs. + + properties: + reg: + description: AHCI SATA port identifier + maxItems: 1 + + phys: + description: Individual AHCI SATA port PHY + maxItems: 1 + + phy-names: + description: AHCI SATA port PHY ID + maxItems: 1 + + target-supply: + description: Power regulator for SATA port target device + + required: + - reg + + additionalProperties: true + +required: + - reg + - interrupts + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml index 9304e4731965..76075d3c8987 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -36,8 +36,7 @@ select: - compatible allOf: - - $ref: "sata-common.yaml#" - + - $ref: "ahci-common.yaml#" properties: compatible: @@ -69,90 +68,35 @@ properties: maxItems: 1 clocks: - description: - Clock IDs array as required by the controller. minItems: 1 maxItems: 3 clock-names: - description: - Names of clocks corresponding to IDs in the clock property. minItems: 1 maxItems: 3 interrupts: maxItems: 1 - ahci-supply: - description: - regulator for AHCI controller - - phy-supply: - description: - regulator for PHY power - - phys: - description: - List of all PHYs on this controller - maxItems: 1 - - phy-names: - description: - Name specifier for the PHYs - maxItems: 1 - - ports-implemented: - $ref: '/schemas/types.yaml#/definitions/uint32' - description: | - Mask that indicates which ports that the HBA supports - are available for software to use. Useful if PORTS_IMPL - is not programmed by the BIOS, which is true with - some embedded SoCs. - maximum: 0x1f - power-domains: maxItems: 1 resets: maxItems: 1 - target-supply: - description: - regulator for SATA target power - -required: - - compatible - - reg - - interrupts - patternProperties: "^sata-port@[0-9a-f]+$": type: object - additionalProperties: false - description: - Subnode with configuration of the Ports. - - properties: - reg: - maxItems: 1 - - phys: - maxItems: 1 - - phy-names: - maxItems: 1 - - target-supply: - description: - regulator for SATA target power - - required: - - reg anyOf: - required: [ phys ] - required: [ target-supply ] +required: + - compatible + - reg + - interrupts + unevaluatedProperties: false examples: -- 2.35.1