Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Wed, 4 May 2022 14:22:44 -0700 (PDT)
From:   matthew.gerlach@linux.intel.com
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
cc:     dinguyen@kernel.org, robh+dt@kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        krzysztof.kozlowski+dt@linaro.org
Subject: Re: [PATCH v2 3/3] arm64: dts: intel: add device tree for n6000
In-Reply-To: <608ba746-9116-3f36-d640-07eb8b5d793e@linaro.org>
Message-ID: <alpine.DEB.2.22.394.2205041415420.2669897@rhweight-WRK1>
References: <20220503194546.1287679-1-matthew.gerlach@linux.intel.com> <20220503194546.1287679-4-matthew.gerlach@linux.intel.com> <608ba746-9116-3f36-d640-07eb8b5d793e@linaro.org>
User-Agent: Alpine 2.22 (DEB 394 2020-01-19)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII; format=flowed
Precedence: bulk


On Wed, 4 May 2022, Krzysztof Kozlowski wrote:

> On 03/05/2022 21:45, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Add a device tree for the n6000 instantiation of Agilex
>> Hard Processor System (HPS).
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
>> +
>> +	soc {
>> +		agilex_hps_bridges: bus@80000000 {
>> +			compatible = "simple-bus";
>> +			reg = <0x80000000 0x60000000>,
>> +				<0xf9000000 0x00100000>;
>> +			reg-names = "axi_h2f", "axi_h2f_lw";
>> +			#address-cells = <0x2>;
>> +			#size-cells = <0x1>;
>> +			ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
>> +
>> +			hps_cp_eng@0 {
>
> No underscores in node names.  dtc W=1 should complain about it.

I will remove the underscores in the name.  I didn't see a complaint when 
I compiled it with "make W=1" in the kernel tree.

> The node name should be generic, matching class of a device. What is
> this exactly?

The component is a specialized IP block instantiated in the FPGA directly 
connected to the HPS.  In one sense the IP block is a simple DMA 
controller, but it also has some registers for hand shaking between the 
HPS and a host processor connected to the FPGA via PCIe.  Should I call 
the node, dma@0?

Thanks for your review,
Matthew

> > Best regards,
> Krzysztof
>