Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp2558454iob; Fri, 6 May 2022 05:45:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyxWtT074l2kb4CuztROSvPdzzEozTEJZlc4TkL1e4SH5YTdtdO25BmvUjwVYshWGrq6Z+r X-Received: by 2002:a17:906:a383:b0:6f5:132c:1a14 with SMTP id k3-20020a170906a38300b006f5132c1a14mr2814746ejz.21.1651841125044; Fri, 06 May 2022 05:45:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651841125; cv=none; d=google.com; s=arc-20160816; b=CYq0TdY/nW8OErE2Xzz1JNvVA97IkWU85A16RqOc50gW1hM7da8ihDJffeyklTdG5H +q3DxWQdTVuw80VWPoa7FDtzRO2zUG67zfyHUWCeeGjdLK/TckT/p0i/dz3Tx/NW1iLh vOWwidE43Swk9p3TAGsQXvR9c5N1bubAubeZcsxhZvav9sxTi6h5DKe7Tlu6N+RySno4 /Q7z6vdxb4zo1zGsD53ej93gL0UZs+7x3+gghU80XVwf0f5SH680E9mqcW6OhhOfZgiT f9WfxUvAC0KeIBBtkbKuaPib/pZDBj3keXnURO+sMymni+pQzvDPUpoHm4ttL6vwjw+1 vNWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id:dkim-signature; bh=SfFRyNG4hERL+TTomH08jiy/yMmdir6j259/R+4NcYg=; b=jJt6bJh8abpnfLlIchMcGGScrsYGjgkB9R/VgNeUK8YPi7t2S0BABGEqc6JJiQah5B ftCP3d63/3763MFP4NST0jTQIHy8acWlZSIhlVxSXXQ62W4sjhBUGKPdO9UdSCppdbwj ExZ//51XOAzEAkkLOayMn6MA22ZIs0w0XDYHuI6/AdttXJ9jkXL5yvwXVOpoZHLDe6xU sI8944mhQlEEg3r2Uc39rH3PlSCtCvXoj3SudxhaGh8v8G3ZR+P2yiSN2+vNIGl1XojM H9ZutvpLh6JrnWIaKJ1S6epa7yWUGp/6wbfotljYMxi4pXKbc7Rab7eBs2KabJ5/pAaK bpFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=KXHFtCFA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f30-20020a50d55e000000b00427c66840c4si4429600edj.325.2022.05.06.05.45.01; Fri, 06 May 2022 05:45:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=KXHFtCFA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234650AbiEDCFq (ORCPT + 99 others); Tue, 3 May 2022 22:05:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344015AbiEDCCn (ORCPT ); Tue, 3 May 2022 22:02:43 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D9BC2610B; Tue, 3 May 2022 18:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651629532; x=1683165532; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=SfFRyNG4hERL+TTomH08jiy/yMmdir6j259/R+4NcYg=; b=KXHFtCFAw1/YNdZS5bSmXPkpPbq1Ttr6ag/99PSHTabw2v+00+Tz0VK8 2UTFkcEv1sxw6sOM0UwC5C/OyxXAGdG3EJ2VS62cU6YMqWZi9Y3eEpEUi KsdISC+kGoGPMXd72f35yC0FJWzCa+zBAbvLBNyy/p0I/O77taN08jBK6 U=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 03 May 2022 18:58:51 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 18:58:51 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 18:58:51 -0700 Received: from [10.50.60.188] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 18:58:48 -0700 Message-ID: Date: Wed, 4 May 2022 07:28:43 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH 2/2] soc: qcom: llcc: Add sc8180x and sc8280xp configurations Content-Language: en-US To: Bjorn Andersson CC: Rob Herring , Krzysztof Kozlowski , , , References: <20220502215406.612967-1-bjorn.andersson@linaro.org> <20220502215406.612967-3-bjorn.andersson@linaro.org> From: Sai Prakash Ranjan In-Reply-To: <20220502215406.612967-3-bjorn.andersson@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/3/2022 3:24 AM, Bjorn Andersson wrote: > Add LLCC configuration data for the SC8180X and SC8280XP platforms, > based on the downstream tables. > > Signed-off-by: Bjorn Andersson > --- > > Changs since v1: > - Updated tables according to documentation - thanks Sai! > > drivers/soc/qcom/llcc-qcom.c | 60 ++++++++++++++++++++++++++++++ > include/linux/soc/qcom/llcc-qcom.h | 2 + > 2 files changed, 62 insertions(+) > > diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c > index 85ba8209b182..4b143cf7b4ce 100644 > --- a/drivers/soc/qcom/llcc-qcom.c > +++ b/drivers/soc/qcom/llcc-qcom.c > @@ -130,6 +130,50 @@ static const struct llcc_slice_config sc7280_data[] = { > { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, > }; > > +static const struct llcc_slice_config sc8180x_data[] = { > + { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 }, > + { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 }, > + { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 }, > + { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, > + { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, > + { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 }, > +}; > + > +static const struct llcc_slice_config sc8280xp_data[] = { > + { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, > + { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, > + { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, > + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, > + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, > + { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, > + { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, > + { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, > +}; > + > static const struct llcc_slice_config sdm845_data[] = { > { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, > { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, > @@ -276,6 +320,20 @@ static const struct qcom_llcc_config sc7280_cfg = { > .reg_offset = llcc_v1_2_reg_offset, > }; > > +static const struct qcom_llcc_config sc8180x_cfg = { > + .sct_data = sc8180x_data, > + .size = ARRAY_SIZE(sc8180x_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_2_reg_offset, > +}; > + > +static const struct qcom_llcc_config sc8280xp_cfg = { > + .sct_data = sc8280xp_data, > + .size = ARRAY_SIZE(sc8280xp_data), > + .need_llcc_cfg = true, > + .reg_offset = llcc_v1_2_reg_offset, > +}; > + > static const struct qcom_llcc_config sdm845_cfg = { > .sct_data = sdm845_data, > .size = ARRAY_SIZE(sdm845_data), > @@ -741,6 +799,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) > static const struct of_device_id qcom_llcc_of_match[] = { > { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, > { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, > + { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, > + { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, > { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, > { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, > { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, > diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h > index 0bc21ee58fac..9ed5384c5ca1 100644 > --- a/include/linux/soc/qcom/llcc-qcom.h > +++ b/include/linux/soc/qcom/llcc-qcom.h > @@ -29,6 +29,8 @@ > #define LLCC_AUDHW 22 > #define LLCC_NPU 23 > #define LLCC_WLHW 24 > +#define LLCC_PIMEM 25 > +#define LLCC_DRE 26 > #define LLCC_CVP 28 > #define LLCC_MODPE 29 > #define LLCC_APTCM 30 Reviewed-by: Sai Prakash Ranjan (Note: LLCC_PIMEM isn't used now, but I guess doesn't hurt much to be included in header) Thanks, Sai