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Date:   Fri, 06 May 2022 11:25:14 -0000
From:   irqchip-bot for Pali =?utf-8?q?Roh=C3=A1r?= 
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To:     linux-kernel@vger.kernel.org
Subject: [irqchip: irq/irqchip-next] irqchip/armada-370-xp: Do not touch
 Performance Counter Overflow on A375, A38x, A39x
Cc:     pali@kernel.org, stable@vger.kernel.org,
        Andrew Lunn <andrew@lunn.ch>, Marc Zyngier <maz@kernel.org>,
        tglx@linutronix.de
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The following commit has been merged into the irq/irqchip-next branch of irqc=
hip:

Commit-ID:     a3d66a76348daf559873f19afc912a2a7c2ccdaf
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platfo=
rms/a3d66a76348daf559873f19afc912a2a7c2ccdaf
Author:        Pali Roh=C3=A1r <pali@kernel.org>
AuthorDate:    Mon, 25 Apr 2022 13:37:05 +02:00
Committer:     Marc Zyngier <maz@kernel.org>
CommitterDate: Fri, 06 May 2022 12:18:37 +01:00

irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38=
x, A39x

Register ARMADA_370_XP_INT_FABRIC_MASK_OFFS is Armada 370 and XP specific
and on new Armada platforms it has different meaning. It does not configure
Performance Counter Overflow interrupt masking. So do not touch this
register on non-A370/XP platforms (A375, A38x and A39x).

Signed-off-by: Pali Roh=C3=A1r <pali@kernel.org>
Cc: stable@vger.kernel.org
Fixes: 28da06dfd9e4 ("irqchip: armada-370-xp: Enable the PMU interrupts")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425113706.29310-1-pali@kernel.org
---
 drivers/irqchip/irq-armada-370-xp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada=
-370-xp.c
index c877285..ee18eb3 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -327,7 +327,16 @@ static inline int armada_370_xp_msi_init(struct device_n=
ode *node,
=20
 static void armada_xp_mpic_perf_init(void)
 {
-	unsigned long cpuid =3D cpu_logical_map(smp_processor_id());
+	unsigned long cpuid;
+
+	/*
+	 * This Performance Counter Overflow interrupt is specific for
+	 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
+	 */
+	if (!of_machine_is_compatible("marvell,armada-370-xp"))
+		return;
+
+	cpuid =3D cpu_logical_map(smp_processor_id());
=20
 	/* Enable Performance Counter Overflow interrupts */
 	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),