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Message-ID: <f41e8177-dbda-a03a-299e-d18ee5a5f459@quicinc.com>
Date:   Fri, 6 May 2022 18:52:51 +0530
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Subject: Re: [PATCHv14 2/9] coresight: etm4x: Use asm-generic IO memory
 barriers
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To:     Suzuki K Poulose <suzuki.poulose@arm.com>, <arnd@arndb.de>,
        <catalin.marinas@arm.com>, <rostedt@goodmis.org>
CC:     <gregkh@linuxfoundation.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <maz@kernel.org>, <quic_psodagud@quicinc.com>,
        <quic_tsoni@quicinc.com>, <will@kernel.org>,
        Mathieu Poirier <mathieu.poirier@linaro.org>
References: <cover.1651663123.git.quic_saipraka@quicinc.com>
 <0d76de0ecc0aa7cb01fd8b8863a8e567abd4410b.1651663123.git.quic_saipraka@quicinc.com>
 <483bb401-13e6-8c52-4b5f-f3c635b9ad46@arm.com>
 <b44a0e0b-ee86-3b08-0103-3ccee94e3270@quicinc.com>
 <687b78b5-5671-5317-ce9e-98720bb533fa@arm.com>
From:   Sai Prakash Ranjan <quic_saipraka@quicinc.com>
In-Reply-To: <687b78b5-5671-5317-ce9e-98720bb533fa@arm.com>
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On 5/6/2022 2:51 PM, Suzuki K Poulose wrote:
> On 06/05/2022 04:02, Sai Prakash Ranjan wrote:
>> Hi Suzuki,
>>
>> On 5/6/2022 5:14 AM, Suzuki K Poulose wrote:
>>> Hi,
>>>
>>> On 04/05/2022 12:28, Sai Prakash Ranjan wrote:
>>>> Per discussion in [1], it was decided to move to using architecture
>>>> independent/asm-generic IO memory barriers to have just one set of
>>>> them and deprecate use of arm64 specific IO memory barriers in driver
>>>> code. So replace current usage of __io_rmb()/__iowmb() in drivers to
>>>> __io_ar()/__io_bw().
>>>>
>>>> [1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/
>>>>
>>>
>>> Looking at the dis-assembly it looks like in effect they are slightly
>>> different for arm64.
>>>
>>> i.e., before this patch we had
>>>
>>> "dmb osh{ld/st}"
>>>
>>> and after the patch we have :
>>>
>>> "dsb {ld/st}"
>>>
>>> Is this really what we want ? I don't think this is desirable.
>>>
>>> Suzuki
>>>
>>
>> No, this is not supposed to happen and I do not see how it could happen.
>> __io_ar() is defined as __iormb() and __io_bw() is __iowmb().
>>
>> I checked the disassembly in both case with MMIO trace off/on with __etm4_cpu_save()
>> as below and saw the same number of "dmb"s.
>>
>> aarch64-linux-gnu-gdb -batch -ex "disassemble/rs __etm4_cpu_save" vmlinux-without-mmio
>> aarch64-linux-gnu-gdb -batch -ex "disassemble/rs __etm4_cpu_save" vmlinux-with-mmio
>>
>> Can you tell me how are you validating if I am missing something?
>
> Apologies, I was missing the patch in this series, which adds
> the arm64 definition for __io_ar/__io_bw. (hint: Please Cc
> the affected subsystem in the Cover letter for the series, so
> we know what the intention of the changes are).
>

Sure, I will keep this in mind, apologies for the confusion.

> With the patch1, yes this makes sense to me. Otherwise, __io_ar()
> is default to rmb() which implies dsb ld.
>
> With that said,
>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Thanks,
Sai