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[209.85.128.176]) by smtp.gmail.com with ESMTPSA id l14-20020ac84a8e000000b002f39b99f68dsm417304qtq.39.2022.05.04.23.56.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 May 2022 23:56:05 -0700 (PDT) Received: by mail-yw1-f176.google.com with SMTP id 00721157ae682-2ef5380669cso38504037b3.9; Wed, 04 May 2022 23:56:05 -0700 (PDT) X-Received: by 2002:a81:913:0:b0:2f7:c833:f304 with SMTP id 19-20020a810913000000b002f7c833f304mr23117982ywj.283.1651733765108; Wed, 04 May 2022 23:56:05 -0700 (PDT) MIME-Version: 1.0 References: <20220504142333.8844-1-guozhengkui@vivo.com> In-Reply-To: <20220504142333.8844-1-guozhengkui@vivo.com> From: Geert Uytterhoeven Date: Thu, 5 May 2022 08:55:53 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] clk: renesas: rzg2l: remove repeated data To: Guo Zhengkui Cc: Michael Turquette , Stephen Boyd , Linux-Renesas , linux-clk , Linux Kernel Mailing List , zhengkui_guo@outlook.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RDNS_NONE, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Guo, On Wed, May 4, 2022 at 4:24 PM Guo Zhengkui wrote: > Remove a repeated CPG_SIPLL5_CLK1_REFDIV_WEN. > > Signed-off-by: Guo Zhengkui Thanks for your patch! > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -601,9 +601,8 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, > > /* Output clock setting 1 */ > writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_REFDIV_WEN | > - CPG_SIPLL5_CLK1_REFDIV_WEN | (params.pl5_postdiv1 << 0) | This is not correct: one of the CPG_SIPLL5_CLK1_REFDIV_WENs should have been CPG_SIPLL5_CLK1_POSTDIV2_WEN. > - (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8), > - priv->base + CPG_SIPLL5_CLK1); > + (params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) | > + (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1); > > /* Output clock setting, SSCG modulation value setting 3 */ > writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3); So I'm going for Wan's fix instead https://lore.kernel.org/r/20220504142058.18704-1-wanjiabing@vivo.com/ Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds