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[23.128.96.19]) by mx.google.com with ESMTPS id g62-20020a636b41000000b003c144fa99cdsi12445534pgc.543.2022.05.08.19.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 19:58:11 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0693782D39; Sun, 8 May 2022 19:56:58 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356636AbiEELJP convert rfc822-to-8bit (ORCPT + 99 others); Thu, 5 May 2022 07:09:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356545AbiEELJO (ORCPT ); Thu, 5 May 2022 07:09:14 -0400 Received: from mout.kundenserver.de (mout.kundenserver.de [212.227.126.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A03F13D68; Thu, 5 May 2022 04:05:29 -0700 (PDT) Received: from mail-wr1-f43.google.com ([209.85.221.43]) by mrelayeu.kundenserver.de (mreue009 [213.165.67.97]) with ESMTPSA (Nemesis) id 1N6bsM-1ntcJS163q-0182Xn; Thu, 05 May 2022 13:05:28 +0200 Received: by mail-wr1-f43.google.com with SMTP id b19so5599157wrh.11; Thu, 05 May 2022 04:05:28 -0700 (PDT) X-Gm-Message-State: AOAM532/XuQ+VxCW+RCJlBYDifqthSn+DzppiqEiO0MXfdy9Lw2E8mwU AmTRs8BJlhS1+ChRbtvn1xzCo8mnDEnJc7hJUME= X-Received: by 2002:a5d:49cb:0:b0:20a:cee3:54fc with SMTP id t11-20020a5d49cb000000b0020acee354fcmr19580488wrs.12.1651748727768; Thu, 05 May 2022 04:05:27 -0700 (PDT) MIME-Version: 1.0 References: <20220430153626.30660-1-palmer@rivosinc.com> <20220430153626.30660-3-palmer@rivosinc.com> <7375410.EvYhyI6sBW@diego> In-Reply-To: <7375410.EvYhyI6sBW@diego> From: Arnd Bergmann Date: Thu, 5 May 2022 13:05:11 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 2/7] asm-generic: qspinlock: Indicate the use of mixed-size atomics To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: Arnd Bergmann , linux-riscv , Guo Ren , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Paul Walmsley , Palmer Dabbelt , Albert Ou , Greg KH , Sudip Mukherjee , "Maciej W. Rozycki" , Jisheng Zhang , linux-csky@vger.kernel.org, Linux Kernel Mailing List , Openrisc , linux-arch , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Provags-ID: V03:K1:QysLADnJBunexLp/VCtIkDOzKmjNjjUU2GxeczuxJ6drISdwCcZ sEAlEW8THoAaog2NWGf0dK6cn1QMdZU1Y0xy3ph/vSNkTng9Csu++f7XgDol4y+nBjXU4CD x+ymU3d1p/NSwHjHWpb3AN+XquqUvSAyQR9Bg5roWAaHcSn+tY17mxJAC7WmXtMNh6SHUtc rADN6ZPKHDshur69Frhmw== X-UI-Out-Filterresults: notjunk:1;V03:K0:TjhMztt8YDc=:4dnBppYatAR7PxXLHcu0eo yFaNulrHg6PxYbAlJi5oFrgK9d2ktnedOe3BxGnYgdV333sxEmIiZtvkOrwKGQty5J9Q3HRvw mxuygVf/EKkVsqBKdv4ymcdQ/9lPIssIv/RSUNbQql7WEb3QRddo7lKjLb9v61vofV1wwDGQT lwTUa/aBCTw1z6g0slx213YmzOb8zkN4FOAEYp10fnJaw4ra+xjHKynTWCe0sSSdtJ6z2id4x CERoJaVnoTFzh5Ms7328cFAtAYuV5OAAPo7DUVyTSQJ+LfJIu3jODNK6ZjFE0M9F2x2NqVxH7 QtvLGaCFkEqvBRUKQLBiV/VkviNW6Qg46JzeCx2L03mGGHhAOVqZ33Fq23ChS5R5UTCfZACjA sfIHuVhYToKIhq7qp/3c9aD+RGWlwjZmWuDNbuXoXjrinkt5bJIUYUkQbr3rJdAHSobISsWUO 86aOpf2cv3OcNfpVL1RG6NGll2R7r/0YmAeMlQOS+OKm8aBsMsnut/Ynf7g7ghZ+o6zwph60B y9A419lJMhUv2Ju528xhjq+GBFrYlskHssSxN9wJb8vW9NuH6qOGs1YXOCWmN++5Omqs0A7n4 9jk71gJDgFTTtsITTzbGALziXOuUv7ybUy/S6X0odsB8Mde8O3/4gnpCnDciJekfKq0vpiFHm 5tyh3SCPUHYwQkjns6wJqi3fu1420CLXTz0HCP4TfPhIw1KdzSqZ3GOrSxP8X6elweiEz6PTt WBvoftQcRQy2sRPRNyXyIeMxApzdSJDfbs2iT5zoyRaenRNrKmyEbr3XVVBavjcd3F5lrQY8d Zm4K0sx3qhPTkkL1m8Wmfpg9b8g8R2H58GYmUehIZgLk3k6SIQ= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RDNS_NONE, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 4, 2022 at 2:02 PM Heiko Stübner wrote: > > index d74b13825501..95be3f3c28b5 100644 > > --- a/include/asm-generic/qspinlock.h > > +++ b/include/asm-generic/qspinlock.h > > @@ -2,6 +2,37 @@ > > /* > > * Queued spinlock > > * > > + * A 'generic' spinlock implementation that is based on MCS locks. An > > _For_ an architecture that's ... ? > > > + * architecture that's looking for a 'generic' spinlock, please first consider > > + * ticket-lock.h and only come looking here when you've considered all the > > + * constraints below and can show your hardware does actually perform better > > + * with qspinlock. > > + * > > + * > > double empty line is probably not necessary > I've applied the series to the asm-generic tree now, and edited both the above as you suggested in the process, to save Palmer the v5. Arnd