Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18;
From:   =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
To:     Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Gregory Clement <gregory.clement@bootlin.com>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= <kw@linux.com>,
        =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Cc:     linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/6] PCI: mvebu: Add support for PME and AER interrupts
Date:   Fri,  6 May 2022 15:40:23 +0200
Message-Id: <20220506134029.21470-1-pali@kernel.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk

mvebu PCIe PME and AER interrupts are reported via PCIe summary
interrupt. PCIe summary interrupt is reported via mvebu MPIC SoC error
summary interrupt. And MPIC SoC error summary interrupt is reported via
MPIC IRQ 4.

This patch series implements support for interrupts in MPIC SoC error
hierarchy in irq-armada-370-xp.c driver and support for interrupts in
mvebu PCIe hierarchy in pci-mvebu.c.

Finally PCIe PME and AER interrupts are routed to the correct PCIe Root
Port, which allows kernel PME and AER drivers to take care of them.

Tested on A385 board and kernel PME and AER drivers works correctly:

[    0.898482] pcieport 0000:00:01.0: PME: Signaling with IRQ 61
[    0.904422] pcieport 0000:00:01.0: AER: enabled with IRQ 61
[    0.910113] pcieport 0000:00:02.0: enabling device (0140 -> 0142)
[    0.916299] pcieport 0000:00:02.0: PME: Signaling with IRQ 62
[    0.922216] pcieport 0000:00:02.0: AER: enabled with IRQ 62
[    0.927917] pcieport 0000:00:03.0: enabling device (0140 -> 0142)
[    0.934090] pcieport 0000:00:03.0: PME: Signaling with IRQ 63
[    0.940006] pcieport 0000:00:03.0: AER: enabled with IRQ 63

This change finally allows to debug PCIe issues on A385 boards.

Pali Rohár (6):
  dt-bindings: irqchip: armada-370-xp: Update information about MPIC SoC
    Error
  irqchip/armada-370-xp: Implement SoC Error interrupts
  ARM: dts: armada-38x.dtsi: Add node for MPIC SoC Error IRQ controller
  dt-bindings: PCI: mvebu: Update information about summary interrupt
  PCI: mvebu: Implement support for interrupts on emulated bridge
  ARM: dts: armada-385.dtsi: Add definitions for PCIe summary interrupts

 .../marvell,armada-370-xp-mpic.txt            |   9 +
 .../devicetree/bindings/pci/mvebu-pci.txt     |   1 +
 arch/arm/boot/dts/armada-385.dtsi             |  20 +-
 arch/arm/boot/dts/armada-38x.dtsi             |   5 +
 drivers/irqchip/irq-armada-370-xp.c           | 213 +++++++++++++++++-
 drivers/pci/controller/pci-mvebu.c            | 208 +++++++++++++++--
 6 files changed, 426 insertions(+), 30 deletions(-)

-- 
2.20.1