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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id y11-20020a170902cacb00b00158f04afd74si8897642pld.146.2022.05.08.23.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 23:24:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=E2NtPqVi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B846017789B; Sun, 8 May 2022 23:22:56 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387301AbiEFADI (ORCPT + 99 others); Thu, 5 May 2022 20:03:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385624AbiEFACO (ORCPT ); Thu, 5 May 2022 20:02:14 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B61D612BD for ; Thu, 5 May 2022 16:57:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651795076; x=1683331076; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=L3Ao7/ADM/27W4au5Ct5JCZDRw2G77dHHek57JRUTvg=; b=E2NtPqViFWrn2atGGZYkTXkyMPghh01m6m/aaUYnjDRPlyrpGbPSNngE UROZnMTxsZlxcj7P/G7WP/mXQ10bKYo30mllB8ulfdqkHLjhX83LgEufs cYp96O3Pdsfq+TMstygsrenDXUP9CCJWAvpzyPjOeG563AXruixSxvQw4 NhrbxMk0w93hYcc3t95G3vFREDWZplKDti8NYIp2uO4H2QqwxqpQ9Cs4z Wgbb8RiovDg1QIvouwOL74ff5B9ZVvMHxtVmWIanP5RZXqXX8lbG7tqnY FgsBUd101imyK2fRhEvDcFrX3O2R+qP8BKDqnHHt+uUBw9FVFVZvrSVnW Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="250283651" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="250283651" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 16:57:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="694914422" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga004.jf.intel.com with ESMTP; 05 May 2022 16:57:53 -0700 From: Ricardo Neri To: Thomas Gleixner , x86@kernel.org Cc: Tony Luck , Andi Kleen , Stephane Eranian , Andrew Morton , Joerg Roedel , Suravee Suthikulpanit , David Woodhouse , Lu Baolu , Nicholas Piggin , "Ravi V. Shankar" , Ricardo Neri , iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v6 21/29] x86/nmi: Add an NMI_WATCHDOG NMI handler category Date: Thu, 5 May 2022 17:00:00 -0700 Message-Id: <20220506000008.30892-22-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> References: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a NMI_WATCHDOG as a new category of NMI handler. This new category is to be used with the HPET-based hardlockup detector. This detector does not have a direct way of checking if the HPET timer is the source of the NMI. Instead, it indirectly estimates it using the time-stamp counter. Therefore, we may have false-positives in case another NMI occurs within the estimated time window. For this reason, we want the handler of the detector to be called after all the NMI_LOCAL handlers. A simple way of achieving this with a new NMI handler category. Cc: Andi Kleen Cc: Andrew Morton Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Cc: x86@kernel.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v5: * Updated to call instrumentation_end() as per f051f6979550 ("x86/nmi: Protect NMI entry against instrumentation") Changes since v4: * None Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/nmi.h | 1 + arch/x86/kernel/nmi.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 1cb9c17a4cb4..4a0d5b562c91 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -28,6 +28,7 @@ enum { NMI_UNKNOWN, NMI_SERR, NMI_IO_CHECK, + NMI_WATCHDOG, NMI_MAX }; diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index e73f7df362f5..fde387e0812a 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -61,6 +61,10 @@ static struct nmi_desc nmi_desc[NMI_MAX] = .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock), .head = LIST_HEAD_INIT(nmi_desc[3].head), }, + { + .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[4].lock), + .head = LIST_HEAD_INIT(nmi_desc[4].head), + }, }; @@ -168,6 +172,8 @@ int __register_nmi_handler(unsigned int type, struct nmiaction *action) */ WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head)); WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head)); + WARN_ON_ONCE(type == NMI_WATCHDOG && !list_empty(&desc->head)); + /* * some handlers need to be executed first otherwise a fake @@ -379,6 +385,10 @@ static noinstr void default_do_nmi(struct pt_regs *regs) } raw_spin_unlock(&nmi_reason_lock); + handled = nmi_handle(NMI_WATCHDOG, regs); + if (handled == NMI_HANDLED) + goto out; + /* * Only one NMI can be latched at a time. To handle * this we may process multiple nmi handlers at once to -- 2.17.1