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From:   Peng Fan <peng.fan@nxp.com>
To:     Shawn Guo <shawnguo@kernel.org>,
        "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
CC:     "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH V2 1/3] arm64: dts: freescale: Add i.MX93 dtsi support
Thread-Topic: [PATCH V2 1/3] arm64: dts: freescale: Add i.MX93 dtsi support
Thread-Index: AQHYXulJXLH702QE2Uen3kTORawBGq0P+roAgAMDZFA=
Date:   Sat, 7 May 2022 06:46:16 +0000
Message-ID: <DU0PR04MB94174452A46F14A5C0C1813F88C49@DU0PR04MB9417.eurprd04.prod.outlook.com>
References: <20220503122951.4147636-1-peng.fan@oss.nxp.com>
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 <20220505084404.GF14615@dragon>
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> Subject: Re: [PATCH V2 1/3] arm64: dts: freescale: Add i.MX93 dtsi suppor=
t
>=20
> On Tue, May 03, 2022 at 08:29:49PM +0800, Peng Fan (OSS) wrote:
> ...
> > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi
> > b/arch/arm64/boot/dts/freescale/imx93.dtsi
> > new file mode 100644
> > index 000000000000..ae8daffe3492
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> > @@ -0,0 +1,337 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2022 NXP
> > + */
> > +
> > +#include <dt-bindings/clock/imx93-clock.h> #include
> > +<dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +#include "imx93-pinfunc.h"
> > +
> > +/ {
> > +	interrupt-parent =3D <&gic>;
> > +	#address-cells =3D <2>;
> > +	#size-cells =3D <2>;
> > +
> > +	aliases {
> > +		mmc0 =3D &usdhc1;
> > +		mmc1 =3D &usdhc2;
> > +		mmc2 =3D &usdhc3;
> > +		serial0 =3D &lpuart1;
> > +		serial1 =3D &lpuart2;
> > +		serial2 =3D &lpuart3;
> > +		serial3 =3D &lpuart4;
> > +		serial4 =3D &lpuart5;
> > +		serial5 =3D &lpuart6;
> > +		serial6 =3D &lpuart7;
> > +		serial7 =3D &lpuart8;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells =3D <1>;
> > +		#size-cells =3D <0>;
> > +
> > +		A55_0: cpu@0 {
> > +			device_type =3D "cpu";
> > +			compatible =3D "arm,cortex-a55";
> > +			reg =3D <0x0>;
> > +			enable-method =3D "psci";
> > +			#cooling-cells =3D <2>;
> > +		};
> > +
> > +		A55_1: cpu@100 {
> > +			device_type =3D "cpu";
> > +			compatible =3D "arm,cortex-a55";
> > +			reg =3D <0x100>;
> > +			enable-method =3D "psci";
> > +			#cooling-cells =3D <2>;
> > +		};
> > +
> > +	};
> > +
> > +	osc_32k: clock-osc-32k {
> > +		compatible =3D "fixed-clock";
> > +		#clock-cells =3D <0>;
> > +		clock-frequency =3D <32768>;
> > +		clock-output-names =3D "osc_32k";
> > +	};
> > +
> > +	osc_24m: clock-osc-24m {
> > +		compatible =3D "fixed-clock";
> > +		#clock-cells =3D <0>;
> > +		clock-frequency =3D <24000000>;
> > +		clock-output-names =3D "osc_24m";
> > +	};
> > +
> > +	clk_ext1: clock-ext1 {
> > +		compatible =3D "fixed-clock";
> > +		#clock-cells =3D <0>;
> > +		clock-frequency =3D <133000000>;
> > +		clock-output-names =3D "clk_ext1";
> > +	};
> > +
> > +	psci {
> > +		compatible =3D "arm,psci-1.0";
> > +		method =3D "smc";
> > +	};
> > +
> > +	timer {
> > +		compatible =3D "arm,armv8-timer";
> > +		interrupts =3D <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +		clock-frequency =3D <24000000>;
> > +		arm,no-tick-in-suspend;
> > +		interrupt-parent =3D <&gic>;
> > +	};
> > +
> > +	gic: interrupt-controller@48000000 {
> > +		compatible =3D "arm,gic-v3";
> > +		reg =3D <0 0x48000000 0 0x10000>,
> > +		      <0 0x48040000 0 0xc0000>;
> > +		#interrupt-cells =3D <3>;
> > +		interrupt-controller;
> > +		interrupts =3D <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-parent =3D <&gic>;
> > +	};
> > +
> > +	soc@0 {
>=20
> Why do we need unit-address '@0' here?

I follow other i.MX dtsi, imx8m[q/m/n/q] all has it.

>=20
> > +		compatible =3D "simple-bus";
> > +		#address-cells =3D <1>;
> > +		#size-cells =3D <1>;
> > +		ranges =3D <0x0 0x0 0x0 0x80000000>,
> > +			 <0x28000000 0x0 0x28000000 0x10000000>;
> > +
> > +		aips1: bus@44000000 {
> > +			compatible =3D "fsl,aips-bus", "simple-bus";
> > +			reg =3D <0x44000000 0x800000>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <1>;
> > +			ranges;
> > +
> > +			mu1: mailbox@44230000 {
> > +				compatible =3D "fsl,imx93-mu", "fsl,imx8ulp-mu";
> > +				reg =3D <0x44230000 0x10000>;
> > +				interrupts =3D <GIC_SPI 22
> IRQ_TYPE_LEVEL_HIGH>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			system_counter: timer@44290000 {
> > +				compatible =3D "nxp,sysctr-timer";
> > +				reg =3D <0x44290000 0x30000>;
> > +				interrupts =3D <GIC_SPI 74
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&osc_24m>;
> > +				clock-names =3D "per";
> > +			};
> > +
> > +			lpuart1: serial@44380000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x44380000 0x1000>;
> > +				interrupts =3D <GIC_SPI 19
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART1_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart2: serial@44390000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x44390000 0x1000>;
> > +				interrupts =3D <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART2_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "okay";
>=20
> We only use "okay" status to flip "disabled" device at board level.

Sure.

>=20
> > +			};
> > +
> > +			iomuxc: pinctrl@443c0000 {
> > +				compatible =3D "fsl,imx93-iomuxc";
> > +				reg =3D <0x443c0000 0x10000>;
> > +			};
> > +
> > +			clk: clock-controller@44450000 {
> > +				compatible =3D "fsl,imx93-ccm";
> > +				reg =3D <0x44450000 0x10000>;
> > +				#clock-cells =3D <1>;
> > +				clocks =3D <&osc_32k>, <&osc_24m>,
> <&clk_ext1>;
> > +				clock-names =3D "osc_32k", "osc_24m",
> "clk_ext1";
> > +				status =3D "okay";
> > +			};
> > +
> > +			anatop: anatop@44480000 {
> > +				compatible =3D "fsl,imx93-anatop", "syscon";
> > +				reg =3D <0x44480000 0x10000>;
> > +			};
> > +		};
> > +
> > +		aips2: bus@42000000 {
> > +			compatible =3D "fsl,aips-bus", "simple-bus";
> > +			reg =3D <0x42000000 0x800000>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <1>;
> > +			ranges;
> > +
> > +			mu2: mailbox@42440000 {
> > +				compatible =3D "fsl,imx93-mu", "fsl,imx8ulp-mu";
> > +				reg =3D <0x42440000 0x10000>;
> > +				interrupts =3D <GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart3: serial@42570000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x42570000 0x1000>;
> > +				interrupts =3D <GIC_SPI 68
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART3_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart4: serial@42580000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x42580000 0x1000>;
> > +				interrupts =3D <GIC_SPI 69
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART4_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "okay";
> > +			};
> > +
> > +			lpuart5: serial@42590000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x42590000 0x1000>;
> > +				interrupts =3D <GIC_SPI 70
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART5_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart6: serial@425a0000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x425a0000 0x1000>;
> > +				interrupts =3D <GIC_SPI 71
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART6_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart7: serial@42690000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x42690000 0x1000>;
> > +				interrupts =3D <GIC_SPI 210
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART7_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart8: serial@426a0000 {
> > +				compatible =3D "fsl,imx93-lpuart", "fsl,imx7ulp-
> lpuart";
> > +				reg =3D <0x426a0000 0x1000>;
> > +				interrupts =3D <GIC_SPI 211
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_LPUART8_GATE>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +		};
> > +
> > +		aips3: bus@42800000 {
> > +			compatible =3D "fsl,aips-bus", "simple-bus";
> > +			reg =3D <0x42800000 0x800000>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <1>;
> > +			ranges;
> > +
> > +			usdhc1: mmc@42850000 {
> > +				compatible =3D "fsl,imx93-usdhc", "fsl,imx8mm-
> usdhc";
> > +				reg =3D <0x42850000 0x10000>;
> > +				interrupts =3D <GIC_SPI 86
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_DUMMY>,
> > +					 <&clk IMX93_CLK_DUMMY>,
> > +					 <&clk IMX93_CLK_USDHC1_GATE>;
> > +				clock-names =3D "ipg", "ahb", "per";
> > +				bus-width =3D <8>;
> > +				fsl,tuning-start-tap =3D <20>;
> > +				fsl,tuning-step=3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			usdhc2: mmc@42860000 {
> > +				compatible =3D "fsl,imx93-usdhc", "fsl,imx8mm-
> usdhc";
> > +				reg =3D <0x42860000 0x10000>;
> > +				interrupts =3D <GIC_SPI 87
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_DUMMY>,
> > +					 <&clk IMX93_CLK_DUMMY>,
> > +					 <&clk IMX93_CLK_USDHC2_GATE>;
> > +				clock-names =3D "ipg", "ahb", "per";
> > +				bus-width =3D <4>;
> > +				fsl,tuning-start-tap =3D <20>;
> > +				fsl,tuning-step=3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			usdhc3: mmc@428b0000 {
> > +				compatible =3D "fsl,imx93-usdhc", "fsl,imx8mm-
> usdhc";
> > +				reg =3D <0x428b0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 205
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&clk IMX93_CLK_DUMMY>,
> > +					 <&clk IMX93_CLK_DUMMY>,
> > +					 <&clk IMX93_CLK_USDHC3_GATE>;
> > +				clock-names =3D "ipg", "ahb", "per";
> > +				bus-width =3D <4>;
> > +				fsl,tuning-start-tap =3D <20>;
> > +				fsl,tuning-step=3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +		};
> > +
> > +		gpio2: gpio@43810000 {
> > +			compatible =3D "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
> > +			reg =3D <0x43810080 0x1000>, <0x43810040 0x40>;
>=20
> 'make W=3D1 dtbs' gives the following warnings.
>=20
> ../arch/arm64/boot/dts/freescale/imx93.dtsi:289.24-299.5: Warning
> (simple_bus_reg): /soc@0/gpio@43810000: simple-bus unit address format
> error, expected "43810080"
> ../arch/arm64/boot/dts/freescale/imx93.dtsi:301.24-311.5: Warning
> (simple_bus_reg): /soc@0/gpio@43820000: simple-bus unit address format
> error, expected "43820080"
> ../arch/arm64/boot/dts/freescale/imx93.dtsi:313.24-323.5: Warning
> (simple_bus_reg): /soc@0/gpio@43830000: simple-bus unit address format
> error, expected "43830080"
> ../arch/arm64/boot/dts/freescale/imx93.dtsi:325.24-335.5: Warning
> (simple_bus_reg): /soc@0/gpio@47400000: simple-bus unit address format
> error, expected "47400080"

Fix in V3.

>=20
> Shawn
>=20
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			gpio-ranges =3D <&iomuxc 0 32 32>;
> > +		};
> > +
> > +		gpio3: gpio@43820000 {
> > +			compatible =3D "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
> > +			reg =3D <0x43820080 0x1000>, <0x43820040 0x40>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			gpio-ranges =3D <&iomuxc 0 64 32>;
> > +		};
> > +
> > +		gpio4: gpio@43830000 {
> > +			compatible =3D "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
> > +			reg =3D <0x43830080 0x1000>, <0x43830040 0x40>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			gpio-ranges =3D <&iomuxc 0 96 32>;
> > +		};
> > +
> > +		gpio1: gpio@47400000 {
> > +			compatible =3D "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
> > +			reg =3D <0x47400080 0x1000>, <0x47400040 0x40>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			gpio-ranges =3D <&iomuxc 0 0 32>;
> > +		};
> > +	};
> > +};
> > --
> > 2.25.1
> >