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Message-ID: <1b42b5aa-2020-b545-72ab-96ec14ef454a@gmail.com>
Date:   Thu, 5 May 2022 15:40:03 +0200
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Subject: Re: [PATCH v2] arm64: dts: mt8192: Follow binding order for SCP
 registers
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To:     =?UTF-8?B?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= 
        <nfraprado@collabora.com>
Cc:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>, kernel@collabora.com,
        Allen-KH Cheng <allen-kh.cheng@mediatek.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-mediatek@lists.infradead.org
References: <20220504214516.2957504-1-nfraprado@collabora.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
In-Reply-To: <20220504214516.2957504-1-nfraprado@collabora.com>
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On 04/05/2022 23:45, Nícolas F. R. A. Prado wrote:
> The dt-binding for SCP documents the reg-names order as sram, cfg,
> l1tcm. Update the SCP node on the mt8192 devicetree to follow that
> order, which gets rid of a dtbs_check warning. This doesn't change any
> behavior since the SCP driver accesses the memory regions through the
> names anyway.
> 
> Fixes: c63556ec6bfe ("arm64: dts: mt8192: Add SCP node")
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 

Applied thanks!

> ---
> 
> Changes in v2:
> - Added missing Fixes tag
> 
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 26dbe9ecc528..733aec2e7f77 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -699,9 +699,9 @@ spi7: spi@1101e000 {
>   		scp: scp@10500000 {
>   			compatible = "mediatek,mt8192-scp";
>   			reg = <0 0x10500000 0 0x100000>,
> -			      <0 0x10700000 0 0x8000>,
> -			      <0 0x10720000 0 0xe0000>;
> -			reg-names = "sram", "l1tcm", "cfg";
> +			      <0 0x10720000 0 0xe0000>,
> +			      <0 0x10700000 0 0x8000>;
> +			reg-names = "sram", "cfg", "l1tcm";
>   			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
>   			clocks = <&infracfg CLK_INFRA_SCPSYS>;
>   			clock-names = "main";