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Date:   Mon, 9 May 2022 15:05:33 +0800
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Subject: Re: [PATCH v4 5/7] perf/x86/amd/core: Add PerfMonV2 counter control
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To:     Sandipan Das <sandipan.das@amd.com>
Cc:     peterz@infradead.org, bp@alien8.de, dave.hansen@linux.intel.com,
        acme@kernel.org, mark.rutland@arm.com,
        alexander.shishkin@linux.intel.com, namhyung@kernel.org,
        jolsa@kernel.org, tglx@linutronix.de, mingo@redhat.com,
        pbonzini@redhat.com, jmattson@google.com, eranian@google.com,
        puwen@hygon.cn, ananth.narayan@amd.com, ravi.bangoria@amd.com,
        santosh.shukla@amd.com,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        linux-perf-users@vger.kernel.org, x86@kernel.org
References: <cover.1651058600.git.sandipan.das@amd.com>
 <5c30d99af03fff90e2fc3165755d18d14bdb229f.1651058600.git.sandipan.das@amd.com>
From:   Like Xu <like.xu.linux@gmail.com>
In-Reply-To: <5c30d99af03fff90e2fc3165755d18d14bdb229f.1651058600.git.sandipan.das@amd.com>
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On 27/4/2022 7:31 pm, Sandipan Das wrote:

>   static void amd_pmu_add_event(struct perf_event *event)
>   {
>   	if (needs_branch_stack(event))
> @@ -1216,6 +1251,11 @@ static int __init amd_core_pmu_init(void)
>   		x86_pmu.num_counters = ebx.split.num_core_pmc;
>   
>   		amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1;
> +
> +		/* Update PMC handling functions */
> +		x86_pmu.enable_all = amd_pmu_v2_enable_all;
> +		x86_pmu.disable_all = amd_pmu_v2_disable_all;
> +		x86_pmu.enable = amd_pmu_v2_enable_event;
>   	}

Considering the below part of code also run on the PerfMonV2 host

whatever the guest PMU version, how about updating these two use cases as well 
in this patch ?

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 262e39a85031..2f7c62e46314 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -1469,8 +1469,8 @@ void amd_pmu_enable_virt(void)
         cpuc->perf_ctr_virt_mask = 0;

         /* Reload all events */
-       amd_pmu_disable_all();
-       x86_pmu_enable_all(0);
+       amd_pmu.disable_all();
+       amd_pmu.enable_all(0);
  }
  EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);

@@ -1487,7 +1487,7 @@ void amd_pmu_disable_virt(void)
         cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;

         /* Reload all events */
-       amd_pmu_disable_all();
-       x86_pmu_enable_all(0);
+       amd_pmu.disable_all();
+       amd_pmu.enable_all(0);
  }
  EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);