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Date:   Mon, 9 May 2022 11:27:40 +0200
From:   Maxime Ripard <maxime@cerno.tech>
To:     qianfanguijin@163.com
Cc:     linux-sunxi@lists.linux.dev, Rob Herring <robh+dt@kernel.org>,
        Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        "Rafael J . Wysocki" <rafael@kernel.org>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH v1] drivers: cpufreq: sun8i-r40: Add cpufreq support
Message-ID: <20220509092740.qmpizwxappy77ggc@houat>
References: <20220509084853.17068-1-qianfanguijin@163.com>
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On Mon, May 09, 2022 at 04:48:53PM +0800, qianfanguijin@163.com wrote:
> From: qianfan Zhao <qianfanguijin@163.com>
>=20
> OPP table value is get from allwinner lichee 3.10 kernel.
>=20
> Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi     | 47 ++++++++++++++++++++++++++++
>  drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
>  2 files changed, 48 insertions(+)
>=20
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r=
40.dtsi
> index 291f4784e86c..90de119095fa 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -54,6 +54,41 @@ / {
>  	#size-cells =3D <1>;
>  	interrupt-parent =3D <&gic>;
> =20
> +	cpu0_opp_table: opp_table0 {
> +		compatible =3D "operating-points-v2";
> +		opp-shared;
> +
> +		opp-720000000 {
> +			opp-hz =3D /bits/ 64 <720000000>;
> +			opp-microvolt =3D <1000000 1000000 1300000>;
> +			clock-latency-ns =3D <2000000>;
> +		};
> +
> +		opp-912000000 {
> +			opp-hz =3D /bits/ 64 <912000000>;
> +			opp-microvolt =3D <1100000 1100000 1300000>;
> +			clock-latency-ns =3D <2000000>;
> +		};
> +
> +		opp-1008000000 {
> +			opp-hz =3D /bits/ 64 <1008000000>;
> +			opp-microvolt =3D <1160000 1160000 1300000>;
> +			clock-latency-ns =3D <2000000>;
> +		};
> +
> +		opp-1104000000 {
> +			opp-hz =3D /bits/ 64 <1104000000>;
> +			opp-microvolt =3D <1240000 1240000 1300000>;
> +			clock-latency-ns =3D <2000000>;
> +		};
> +
> +		opp-1200000000 {
> +			opp-hz =3D /bits/ 64 <1200000000>;
> +			opp-microvolt =3D <1300000 1300000 1300000>;
> +			clock-latency-ns =3D <2000000>;
> +		};
> +	};
> +

How were these OPPs tested? If you didn't, please test with
https://github.com/ssvb/cpuburn-arm/blob/master/cpufreq-ljt-stress-test

And report the results

Also, U-Boot sets the 1008MHz OPP by default, and the voltage to match.
How is this going to play out on device tree where the CPU regulators
aren't set?

Maxime