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[23.128.96.19]) by mx.google.com with ESMTPS id w5-20020a170902d70500b00158dd229950si11057693ply.573.2022.05.09.05.02.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 05:02:43 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Cg6+le4u; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 162722173DA; Mon, 9 May 2022 04:22:54 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232651AbiEIL0Z (ORCPT + 99 others); Mon, 9 May 2022 07:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233069AbiEIL0T (ORCPT ); Mon, 9 May 2022 07:26:19 -0400 Received: from mail-yw1-x1132.google.com (mail-yw1-x1132.google.com [IPv6:2607:f8b0:4864:20::1132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 019DF1AF8EF; Mon, 9 May 2022 04:22:23 -0700 (PDT) Received: by mail-yw1-x1132.google.com with SMTP id 00721157ae682-2f7c57ee6feso140409107b3.2; Mon, 09 May 2022 04:22:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=JHcyRb0A9TdQ3ZPZeebW28t674FP8onCU6WazLElK4U=; b=Cg6+le4ubJ1hcAxrmpylHiTdhVQUuoVW9aEA+iFxxELX6T+A4h3sE6HzJqz6D1834F Vx852sLUvU75YM1EVCdR4NV8kKrypKVn92RyNlAOS9M/o44QTnUE20FPvKpm1XQxUYJW g//yWu3fDYLTb3vTadJXQak2SIfU1HZVuqSYA+8SMRH0lJUUni9hHCXB+GiXgxj30JQY MPMpNGvS1vf3cEx7wxeGs6k9pFp1EISW9qGofMa6X6OK8pYs754hPRo/DOu9uAAaW7jG NgZlSz7Ib0BwyYgSAhHCydm2MqJkySpOzsONRp9HWwW6epPyZkaSeuT7JdHX8TdYf29i NHbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=JHcyRb0A9TdQ3ZPZeebW28t674FP8onCU6WazLElK4U=; b=THmvn6kXYdofFrj4qm8fQwp5y0YmBbeXk8JFdgXKhbAjztLpacIzRCZbV6c4Lqi2cy 0jKzvNNW5L7jMQPEf2/ZkZmq7sJhc+XUgEzUqkt15sahWYnzNsbP1OSO9BcsTE4Ts1ob lBAhMc3Z83B64rmHlY4j50lwQYRmKk4KisfgjrRepys9sgpUANW5zIu4c2PV2WidvwCw yOCbgq4abS9gfSelI/yp+YBKwWxMtqZbPCPTCdNcMWU4a9C63HJegtrP8xfUneyjhdTF 1iEwjz63do/vRQdxPqQ07+8Voy9fR0HZS6yfJ/h4ui6Uw3HblKBiAbez6vl/nlf6V3FZ CWdA== X-Gm-Message-State: AOAM531AD7NPx3E82HyC6mRERZy8/Tjk4JIxvfdo+JsF9EskP72XhM1a XU7dLV5Uys/b8vp1a4DD6wdYjZ+BnSpUbaJpuDQ= X-Received: by 2002:a05:690c:89:b0:2d7:fb7d:db7 with SMTP id be9-20020a05690c008900b002d7fb7d0db7mr14793757ywb.219.1652095341920; Mon, 09 May 2022 04:22:21 -0700 (PDT) MIME-Version: 1.0 References: <20220507170440.64005-1-linux@fw-web.de> <06157623-4b9c-6f26-e963-432c75cfc9e5@linaro.org> <2509116.Lt9SDvczpP@phil> <41d6b00f-d8ac-ca54-99db-ea99c9049e0a@linaro.org> In-Reply-To: <41d6b00f-d8ac-ca54-99db-ea99c9049e0a@linaro.org> From: Peter Geis Date: Mon, 9 May 2022 07:22:11 -0400 Message-ID: Subject: Re: [PATCH v3 5/6] dt-bindings: net: dsa: make reset optional and add rgmii-mode to mt7531 To: Krzysztof Kozlowski Cc: Frank Wunderlich , Heiko Stuebner , "open list:ARM/Rockchip SoC..." , Frank Wunderlich , linux-mediatek@lists.infradead.org, Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Linux Kernel Network Developers , devicetree , arm-mail-list , Linux Kernel Mailing List , Greg Ungerer , =?UTF-8?Q?Ren=C3=A9_van_Dorst?= , Mauro Carvalho Chehab Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RDNS_NONE, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 9, 2022 at 2:48 AM Krzysztof Kozlowski wrote: > > On 08/05/2022 19:04, Peter Geis wrote: > > On Sun, May 8, 2022 at 8:12 AM Frank Wunderlich wrote: > >>> > >>> I think the issue is more for the description itself. > >>> > >>> Devicetree is only meant to describe the hardware and does in general don't > >>> care how any firmware (Linux-kernel, *BSD, etc) handles it. So going with > >>> "the kernel does it this way" is not a valid reason for a binding change ;-) . > > Exactly. The argument in commit msg was not matching the change, because > driver implementation should not be (mostly) a reason for such changes. > > >>> > >>> Instead in general want to reason that there are boards without this reset > >>> facility and thus make it optional for those. > >> > >> if only the wording is the problem i try to rephrase it from hardware PoV. > >> > >> maybe something like this? > >> > >> https://github.com/frank-w/BPI-R2-4.14/commits/5.18-mt7531-mainline2/Documentation/devicetree/bindings/net/dsa/mediatek%2Cmt7530.yaml > > Looks ok. > > >> > >> Another way is maybe increasing the delay after the reset (to give more time all > >> come up again), but imho it is no good idea resetting the gmac/mdio-bus from the > >> child device. > >> > >> have not looked into the gmac driver if this always does the initial reset to > >> have a "clean state". In this initial reset the switch will be resetted too > >> and does not need an additional one which needs the gmac/mdio initialization > >> to be done again. > > > > For clarification, the reset gpio line is purely to reset the phy. > > If having the switch driver own the reset gpio instead of the gmac > > breaks initialization that means there's a bug in the gmac driver > > handling phy init. > > In testing I've seen issues moving the reset line to the mdio node > > with other phys and the stmmac gmac driver, so I do believe this is > > the case. > > Yes, this seems reasonable, although Frank mentioned that reset is > shared with gmac, so it resets some part of it as well? No, the gpio-reset line is purely to reset the phy. The stmmac gmac driver handles it because it seems initialization failures occur if it's handled by the mdio drivers. I suspect this is due to a difference between when the driver initializes the phy vs when the driver triggers the reset. They had tried to attach the gpio binding to both the gmac node and the mdio node at the same time when only one can own it. Having it owned by the switch driver on the mdio node leads to the same initialization failures we see in other mdio drivers. > > > > > Best regards, > Krzysztof