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Mon, 9 May 2022 09:55:48 -0500 From: Yazen Ghannam To: , CC: , , , , Yazen Ghannam Subject: [PATCH 08/18] EDAC/amd64: Add determine_memory_type() into pvt->ops Date: Mon, 9 May 2022 14:55:24 +0000 Message-ID: <20220509145534.44912-9-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509145534.44912-1-yazen.ghannam@amd.com> References: <20220509145534.44912-1-yazen.ghannam@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 84e6ef3e-585e-4a3f-94b5-08da31cc056a X-MS-TrafficTypeDiagnostic: CH2PR12MB4296:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qU6ULGF3JOrkHQzmPKoNazHaEyp9yblMM7vGCk7Ixtqcwj3fFHcBvkG43dFVplEJIgRs+p78arf9vABjawgOJasZa7Cp1xFUAzUoHdoCjqSrtP0cVJCYdrMUHsk8FzEHu3CAK94TAvmr5+cx8x1cj8QlZkJG+yQEj95OrwjA2DhWMAKVL9ONPpatY/ZJlH9UdmAyeqzGwvZhIwg1NHuhwOIiDAX/CwkS0/AHIse0zJcjAsm25XYbaaAqbWRjLmQt7fZGdLxrdDknqZI5djSt5+OeUQcqNRW6WHyp2qB05uSGKVHXMK1Rvxw7l+OKuvl95+HNjz75iu1oZNa32/nT4+DHlRqsoPglsp0wjj700UJdrPBigvq/c25Qh6ZRjXfjcwKPW0bt1ih7/pxwuvKDUDka8IgcqhUdYCpB1WxuuYiQ84RnS7HG+5iPCCTxtPKtd8nikxUh5SHYDUGNvoaJsw6WYIOp0f3yaW+5anbinrInlceevLYTdq6LiNv92coq0rKeQEW4l8hOwpfGR1lbP/q8pQTHMJ7kS5eBEUuR6pa0lT/SooE8X+mUN3W/rlJIWJd2Hnjn2S+DjCFSHRpxJWYZ9MJIEWq8mkS6nk/pSeqTyiXoXj8F0f0LmWC7S8vTsGsL87zHNHezMsOs36HMx5IchTvgTzlcuL2y07FRZtagSOy+sc0HCR+UmS8HVoxVTpqvIWJHJMUCaKKrcpkkZw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(4326008)(8676002)(83380400001)(70206006)(70586007)(81166007)(40460700003)(2906002)(356005)(336012)(110136005)(36756003)(54906003)(508600001)(6666004)(7696005)(316002)(36860700001)(82310400005)(2616005)(26005)(1076003)(5660300002)(186003)(16526019)(86362001)(8936002)(44832011)(426003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 14:55:55.8431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84e6ef3e-585e-4a3f-94b5-08da31cc056a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4296 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Muralidhara M K GPU Nodes will need to set the EDAC memory type differently than existing systems. A function pointer should be used rather than introduce another branching condition. Prepare for this by adding determine_memory_type() to pvt->ops and set it as needed based on currently supported systems. Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs). Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs). Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 16 +++++++--------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 6e26bbb73f81..a767d8a6bfe8 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1604,7 +1604,7 @@ static void dct_read_base_mask(struct amd64_pvt *pvt) } } -static void determine_memory_type_df(struct amd64_pvt *pvt) +static void umc_determine_memory_type(struct amd64_pvt *pvt) { struct amd64_umc *umc; u32 i; @@ -1641,13 +1641,10 @@ static void determine_memory_type_df(struct amd64_pvt *pvt) } } -static void determine_memory_type(struct amd64_pvt *pvt) +static void dct_determine_memory_type(struct amd64_pvt *pvt) { u32 dram_ctrl, dcsm; - if (pvt->umc) - return determine_memory_type_df(pvt); - switch (pvt->fam) { case 0xf: if (pvt->ext_model >= K8_REV_F) @@ -1697,6 +1694,8 @@ static void determine_memory_type(struct amd64_pvt *pvt) WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); pvt->dram_type = MEM_EMPTY; } + + edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); return; ddr3: @@ -3302,10 +3301,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) pvt->ops->read_base_mask(pvt); - determine_memory_type(pvt); - - if (!pvt->umc) - edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); + pvt->ops->determine_memory_type(pvt); determine_ecc_sym_sz(pvt); } @@ -3763,6 +3759,7 @@ static struct low_ops umc_ops = { .dbam_to_cs = umc_addr_mask_to_cs_size, .prep_chip_selects = umc_prep_chip_selects, .read_base_mask = umc_read_base_mask, + .determine_memory_type = umc_determine_memory_type, }; /* Use Family 16h versions for defaults and adjust as needed below. */ @@ -3772,6 +3769,7 @@ static struct low_ops dct_ops = { .dbam_to_cs = f16_dbam_to_chip_select, .prep_chip_selects = dct_prep_chip_selects, .read_base_mask = dct_read_base_mask, + .determine_memory_type = dct_determine_memory_type, }; static int per_family_init(struct amd64_pvt *pvt) diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index c81cc7f5fc96..da3db0f4f59b 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -470,6 +470,7 @@ struct low_ops { unsigned int cs_mode, int cs_mask_nr); void (*prep_chip_selects)(struct amd64_pvt *pvt); void (*read_base_mask)(struct amd64_pvt *pvt); + void (*determine_memory_type)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, -- 2.25.1