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Date:   Mon, 9 May 2022 16:48:13 +0100
From:   Mark Brown <broonie@kernel.org>
To:     James Clark <james.clark@arm.com>
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-perf-users@vger.kernel.org, german.gomez@arm.com,
        John Garry <john.garry@huawei.com>,
        Will Deacon <will@kernel.org>,
        Mathieu Poirier <mathieu.poirier@linaro.org>,
        Leo Yan <leo.yan@linaro.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@kernel.org>,
        Namhyung Kim <namhyung@kernel.org>, linux-doc@vger.kernel.org
Subject: Re: [PATCH v1 1/6] perf: arm64: Add SVE vector granule register to
 user regs
Message-ID: <Ynk3vTtJApO13peb@sirena.org.uk>
References: <20220509144257.1623063-1-james.clark@arm.com>
 <20220509144257.1623063-2-james.clark@arm.com>
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On Mon, May 09, 2022 at 03:42:49PM +0100, James Clark wrote:
> Dwarf based unwinding in a function that pushes SVE registers onto
> the stack requires the unwinder to know the length of the SVE register
> to calculate the stack offsets correctly. This was added to the Arm
> specific Dwarf spec as the VG pseudo register[1].
>=20
> Add the vector length at position 46 if it's requested by userspace and
> SVE is supported. If it's not supported then fail to open the event.
>=20
> The vector length must be on each sample because it can be changed
> at runtime via a prctl or ptrace call. Also by adding it as a register
> rather than a separate attribute, minimal changes will be required in an
> unwinder that already indexes into the register list.

> +static u64 perf_ext_regs_value(int idx)
> +{
> +	switch (idx) {
> +	case PERF_REG_ARM64_VG:
> +		if (WARN_ON_ONCE(!system_supports_sve()))
> +			return 0;

These WARN_ON_ONCE()s seem a bit loud but I do see they are idiomatic
for this code so

Reviewed-by: Mark Brown <broonie@kernel.org>

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmJ5N70ACgkQJNaLcl1U
h9ARVQf9G0mw/2Bx5k3Bh/9t98gHB+qEtoXMXhzgkJjMUiXzj3E9uwkUmvKNR58B
PkM4MMWPCy3pQAP/Pc0zgLSKyOM30z54SdCucVVRP+ma8+y4+cBUnxvp5462F8x7
mKMbLjp3E1D1vl+4y/nqCOEKctytWfJEMUvMPd36n3Hwt4fg/7gzv14wCaJzZMrk
TZJe/W8LsNFr/pQMpPA5yKgonJKP8QCC97028L1BUq8tNWNMSWp1rtStgwDm6f7d
ZeuCqrHHljaqY9/3QuuX5LBXMr3b3WyrzVdguH1xSDChvnKQHHUpneY0oNUvDFCh
O7zct9SC04onTfuDNr1orFH6uAliQg==
=TX9r
-----END PGP SIGNATURE-----

--kWHxwAIOcGn9XJL6--