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Date:   Tue, 10 May 2022 09:24:10 +0200
From:   =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <clement.leger@bootlin.com>
To:     "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Vivien Didelot <vivien.didelot@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Vladimir Oltean <olteanv@gmail.com>,
        "David S . Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Herve Codina <herve.codina@bootlin.com>,
        =?UTF-8?B?TWlxdcOobA==?= Raynal <miquel.raynal@bootlin.com>,
        Milan Stevanovic <milan.stevanovic@se.com>,
        Jimmy Lalande <jimmy.lalande@se.com>,
        Pascal Eberhard <pascal.eberhard@se.com>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org
Subject: Re: [PATCH net-next v4 04/12] net: pcs: add Renesas MII converter
 driver
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        <20220509131900.7840-5-clement.leger@bootlin.com>
        <Ynl3jpuJFqXLscvE@shell.armlinux.org.uk>
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Le Mon, 9 May 2022 21:20:30 +0100,
"Russell King (Oracle)" <linux@armlinux.org.uk> a =C3=A9crit :

> Hi,
>=20
> On Mon, May 09, 2022 at 03:18:52PM +0200, Cl=C3=A9ment L=C3=A9ger wrote:
> > +#define MIIC_PRCMD			0x0
> > +#define MIIC_ESID_CODE			0x4
> > +
> > +#define MIIC_MODCTRL			0x20
> > +#define MIIC_MODCTRL_SW_MODE		GENMASK(4, 0)
> > +
> > +#define MIIC_CONVCTRL(port)		(0x100 + (port) * 4)
> > +
> > +#define MIIC_CONVCTRL_CONV_SPEED	GENMASK(1, 0)
> > +#define CONV_MODE_10MBPS		0
> > +#define CONV_MODE_100MBPS		BIT(0)
> > +#define CONV_MODE_1000MBPS		BIT(1) =20
>=20
> I think this is an inappropriate use of the BIT() macro. BIT() should
> be used for single bit rather than for field values.
>=20
> You seem to have a two bit field in bits 1 and 0 of a register, which
> has the values of:
> 0 - 10MBPS
> 1 - 100MBPS
> 2 - 1GBPS
>=20
> I'd guess 3 is listed as "undefined", "do not use" or something
> similar?

You are right, this is actually values rather than individual bits.

>=20
> > +
> > +#define MIIC_CONVCTRL_CONV_MODE		GENMASK(3, 2)
> > +#define CONV_MODE_MII			0
> > +#define CONV_MODE_RMII			BIT(0)
> > +#define CONV_MODE_RGMII			BIT(1) =20
>=20
> This looks similar. a 2-bit field in bits 3 and 2 taking values:
> 0 - MII
> 1 - RMII
> 2 - RGMII
>=20
> ...
>=20
> > +static int miic_config(struct phylink_pcs *pcs, unsigned int mode,
> > +		       phy_interface_t interface,
> > +		       const unsigned long *advertising, bool
> > permit) +{
> > +	u32 speed =3D CONV_MODE_10MBPS, conv_mode =3D CONV_MODE_MII,
> > val;
> > +	struct miic_port *miic_port =3D
> > phylink_pcs_to_miic_port(pcs);
> > +	struct miic *miic =3D miic_port->miic;
> > +	int port =3D miic_port->port;
> > +
> > +	switch (interface) {
> > +	case PHY_INTERFACE_MODE_RMII:
> > +		conv_mode =3D CONV_MODE_RMII;
> > +		speed =3D CONV_MODE_100MBPS;
> > +		break;
> > +	case PHY_INTERFACE_MODE_RGMII:
> > +		conv_mode =3D CONV_MODE_RGMII;
> > +		speed =3D CONV_MODE_1000MBPS;
> > +		break;
> > +	case PHY_INTERFACE_MODE_MII: =20
>=20
> I'm not sure why you need to initialise "speed" and "conv_mode" above
> when you could set them here.

It only seemed to me that 0 value was the default init one but I'll
move that in that case.

>=20
> Thanks.=20
>=20