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Date:   Tue, 10 May 2022 08:45:07 +0100
From:   Marc Zyngier <maz@kernel.org>
To:     Haoran Jiang <jianghaoran@kylinos.cn>
Cc:     chenhuacai@kernel.org, jiaxun.yang@flygoat.com, tglx@linutronix.de,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] irqchip/loongson-liointc: 4 cores correspond to different
 interrupt status registers
In-Reply-To: <20220510055303.1907165-1-jianghaoran@kylinos.cn>
References: <20220510055303.1907165-1-jianghaoran@kylinos.cn>
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On 2022-05-10 06:53, Haoran Jiang wrote:
> According to the loongson cpu manual,different cpu cores
> correspond to different interrupt status registers
> 
> Signed-off-by: Haoran Jiang <jianghaoran@kylinos.cn>
> ---
>  drivers/irqchip/irq-loongson-liointc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-loongson-liointc.c
> b/drivers/irqchip/irq-loongson-liointc.c
> index 649c58391618..f4e015b50af0 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -195,7 +195,7 @@ static int __init liointc_of_init(struct 
> device_node *node,
>  		}
> 
>  		for (i = 0; i < LIOINTC_NUM_CORES; i++)
> -			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> +			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
>  	}
> 
>  	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {

You need to provide some more detail:

- where is it documented (something more precise than ¨the loongson cpu 
manual¨)?
- if something doesn´t work today, what is the impact?
- why does it work today without this change?
- if this is a fix, what commit does it fix?
- if this is a fix, does it need to be backported to stable kernels?

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...