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Message-ID: <21bb46ea-6a36-b426-2ca9-4471af5879a1@flygoat.com>
Date:   Tue, 10 May 2022 13:15:17 +0100
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Subject: Re: [PATCH] irqchip/loongson-liointc: 4 cores correspond to different
 interrupt status registers
Content-Language: en-GB
To:     Haoran Jiang <jianghaoran@kylinos.cn>, chenhuacai@kernel.org
Cc:     tglx@linutronix.de, maz@kernel.org, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20220510055303.1907165-1-jianghaoran@kylinos.cn>
From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
In-Reply-To: <20220510055303.1907165-1-jianghaoran@kylinos.cn>
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在 2022/5/10 6:53, Haoran Jiang 写道:
> According to the loongson cpu manual,different cpu cores
> correspond to different interrupt status registers
NAK!

It is intentional to do so.

The per-core ISR register is broken on 3B1500. So we use general ISR 
register here.
The per-core variable is left for LS2K.

Thanks
- Jiaxun
>
> Signed-off-by: Haoran Jiang <jianghaoran@kylinos.cn>
> ---
>   drivers/irqchip/irq-loongson-liointc.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 649c58391618..f4e015b50af0 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -195,7 +195,7 @@ static int __init liointc_of_init(struct device_node *node,
>   		}
>   
>   		for (i = 0; i < LIOINTC_NUM_CORES; i++)
> -			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> +			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
>   	}
>   
>   	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {