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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id zp15-20020a17090684ef00b006f3ef214e56sm5806154ejb.188.2022.05.10.00.08.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 May 2022 00:08:09 -0700 (PDT) Message-ID: <3498643b-cb2e-5685-65e0-7efe1113783f@linaro.org> Date: Tue, 10 May 2022 09:08:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v5 1/2] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Content-Language: en-US To: Chris Packham , "catalin.marinas@arm.com" , "will@kernel.org" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "andrew@lunn.ch" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" Cc: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" References: <20220504044624.951841-1-chris.packham@alliedtelesis.co.nz> <20220504044624.951841-2-chris.packham@alliedtelesis.co.nz> <6770d320-b998-0c9d-3824-0d429834b289@alliedtelesis.co.nz> From: Krzysztof Kozlowski In-Reply-To: <6770d320-b998-0c9d-3824-0d429834b289@alliedtelesis.co.nz> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/05/2022 06:14, Chris Packham wrote: > > Based on the information I have (which isn't much) there is a ref_clk > input that is connected to a 25MHz oscillator and then I'm assuming > these are all generated from that with various dividers. 25MHz is the > only documented option. > > There doesn't appear to be any documented register where I can read out > the divider ratios. It might be nice I could have the fixed osc node and > have these 3 clocks derived with fixed divisors but I don't see any what > of achieving that. OK, but where are the dividers? The ref_clk is outside of SoC, so should be defined in board DTS (at least its rate). If the rest is in the SoC, they are usually part of clock controller, because usually they belong to some power domain or have some clock gating. Best regards, Krzysztof